𝔖 Bobbio Scriptorium

✦ LIBER ✦

A 1-mil/SUP 2/ single-transistor memory cell in n silicon-gate technology

✍ Scribed by Stein, K.U.; Friedrich, H.

Book ID: 119797268
Publisher: IEEE
Year: 1973
Tongue: English
Weight: 913 KB
Volume: 8
Category: Article
ISSN: 0018-9200
DOI: 10.1109/jssc.1973.1050410

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

[IEEE IEEE International Electron Device

[IEEE IEEE International Electron Devices Meeting - San Francisco, CA, USA (8-11 Dec. 2002)] Digest. International Electron Devices Meeting, - A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

✍ Thompson, S.; Anand, N.; Armstrong, M.; Auth, C.; Arcot, B.; Alavi, M.; Bai, P.; 📂 Article 📅 2002 🏛 IEEE ⚖ 276 KB