High-speed sense circuit techniques for
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Akihiko Emori; Kunihiko Suzuki; Seigoh Yukutake; Sadayuki Ookuma; Kinya Mitumoto
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Article
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1998
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John Wiley and Sons
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English
โ 152 KB
This paper describes a high-speed and low-power 1-Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5-mm BiCMOS process technology. By using the quasi-6 module structure, switching between 18-and 36-bit output can be carried out without access delay. Because of the development of a sense cir