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A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques

โœ Scribed by Kitsukawa, G.; Itoh, K.; Hori, R.; Kawajiri, Y.; Watanabe, T.; Kawahara, T.; Matsumoto, T.; Kobayashi, Y.


Book ID
119774127
Publisher
IEEE
Year
1989
Tongue
English
Weight
607 KB
Volume
24
Category
Article
ISSN
0018-9200

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โœ Akihiko Emori; Kunihiko Suzuki; Seigoh Yukutake; Sadayuki Ookuma; Kinya Mitumoto ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› John Wiley and Sons ๐ŸŒ English โš– 152 KB

This paper describes a high-speed and low-power 1-Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5-mm BiCMOS process technology. By using the quasi-6 module structure, switching between 18-and 36-bit output can be carried out without access delay. Because of the development of a sense cir