A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme

✍ Scribed by Perng-Fei Lin; Kuo, J.B.

• Book ID: 119798979
• Publisher: IEEE
• Year: 2002
• Tongue: English
• Weight: 407 KB
• Volume: 37
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/jssc.2002.803023