✦ LIBER ✦

5 V compatibility with 3.3 V-only CMOS ASICs

✍ Scribed by Brian Henderson; Laszlo Gal

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 3.3-V/5-V low power TTL-to-CMOS input

✍ Chi-Chang Wang; Jiin-Chuan Wu 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 195 KB

A 3/5 V compatible I/O buffer

✍ Pelgrom, M.J.M.; Dijkmans, E.C. 📂 Article 📅 1995 🏛 IEEE 🌐 English ⚖ 255 KB

Embedded 5 V-to-3.3 V voltage regulator

✍ den Besten, G.W.; Nauta, B. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 240 KB

1.5 V 1 K-CMOS-RAM with only 8 pins

✍ Meusburger, G. 📂 Article 📅 1981 🏛 IEEE 🌐 English ⚖ 896 KB

3.3 V logic family with 5 V performance

📂 Article 📅 1995 🏛 Elsevier Science 🌐 English ⚖ 66 KB

A low jitter 0.3-165 MHz CMOS PLL freque

✍ Yang, H.C.; Lee, L.K.; Co, R.S. 📂 Article 📅 1997 🏛 IEEE 🌐 English ⚖ 101 KB