3D Interconnect Architectures for Heterogeneous Technologies: Modeling and Optimization

✍ Scribed by Lennart Bamberg, Jan Moritz Joseph, Alberto García-Ortiz, Thilo Pionteck

• Publisher: Springer
• Year: 2022
• Tongue: English
• Leaves: 403
• Edition: 1st ed. 2022
• Category: Library

✦ Synopsis

This book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration. Readers learn about the physical implications of using heterogeneous 3D technologies for SoC integration, while also learning to maximize the 3D-technology gains, through a physical-effect-aware architecture design. The book provides a deep theoretical background covering all abstraction-levels needed to research and architect tomorrow’s 3D-integrated circuits, an extensive set of optimization methods (for power, performance, area, and yield), as well as an open-source optimization and simulation framework for fast exploration of novel designs.

✦ Table of Contents

Preface
Scope
Contribution
Structure
Acknowledgments
Contents
Specific Mathematical Symbols
Specific Units
Specific Symbols Used in Multiple Chapters
Acronyms
Part I Introduction
1 Introduction to 3D Technologies
1.1 Motivation for Heterogeneous 3D ICs
1.1.1 Motivation for 3d: Wire-Length Reduction
1.1.2 Motivation for 3d: Heterogeneous Integration
1.1.3 Examples of Applications
1.2 3D Technologies
1.2.1 Monolithic Integration
1.2.1.1 Advantages and Disadvantages of Monolithic Integration for Architectural Design
1.2.2 tsv-Based Integration
1.2.2.1 tsv Manufacturing
1.2.2.2 tsv-Manufacturing Challenges
1.3 TSV Capacitances—A Problem Resistant to Scaling
1.3.1 Model to Extract the tsv Parasitics
1.3.2 Analysis
1.4 Conclusion
2 Interconnect Architectures for 3D Technologies
2.1 Interconnect Architectures
2.1.1 Networks on Chips (NoCs)
2.1.1.1 Packet Transmission
2.1.1.2 Router Architecture
2.1.1.3 Flow Control
2.1.1.4 Network Topology
2.1.1.5 Routing Algorithm
2.1.1.6 Deadlocks
2.1.1.7 Livelocks
2.1.1.8 Application Mapping
2.1.1.9 Evaluation
2.2 Overview of Interconnect Architectures for 3d ic
2.3 Three-Dimensional Networks on Chips
2.3.1 Performance, Power, and Area
2.4 Conclusion
Part II 3D Technology Modeling
3 High-Level Formulas for the 3D-Interconnect Power Consumption and Performance
3.1 High-Level Formula for the Power Consumption
3.1.1 Effective Capacitance
3.1.2 Power Consumption
3.2 High-Level Formula for the Propagation Delay
3.3 Matrix Formulations
3.4 Evaluation
3.5 Conclusion
4 High-Level Estimation of the 3D-Interconnect Capacitances
4.1 Existing Capacitance Models
4.2 Edge and MOS Effects on the TSV Capacitances
4.2.1 MOS Effect
4.2.2 Edge Effects
4.3 TSV Capacitance Model
4.4 Evaluation
4.4.1 Model Coefficients and Accuracy
4.4.1.1 Experimental Setup
4.4.1.2 Model Coefficients
4.4.1.3 Model Accuracy—Goodness of the Linear Fits
4.4.1.4 Model Accuracy for Complete Capacitance Matrices
4.4.2 Accuracy for the Estimation of the TSV Power Consumption and Performance
4.5 Conclusion
Part III System Modeling
5 Models for Application Traffic and 3D-NoC Simulation
5.1 Overview of the Modeling Approach
5.2 Application Traffic Model
5.3 Simulation Model of 3D NoCs
5.4 Simulator Interfaces
5.5 Conclusion
6 Estimation of the Bit-Level Statistics
6.1 Existing Approaches to Estimate the Bit-Level Statistics for Single Data Streams
6.1.1 Random Data
6.1.2 Normally Distributed Data
6.1.3 One-Hot-Encoded Data
6.1.4 Sequential Data
6.2 Data-Stream Multiplexing
6.2.1 Data-Stream Multiplexing to Reduce the TSV Count
6.2.2 Data-Stream Multiplexing in NoCs
6.2.3 Impact on the Power Consumption
6.3 Estimation of the Bit-Level Statistics in the Presence of Data-Stream Multiplexing
6.4 Evaluation
6.4.1 Model Accuracy
6.4.2 Low-Power Coding
6.5 Conclusion
7 Ratatoskr: A Simulator for NoCs in Heterogeneous 3D SoCs
7.1 Ratatoskr for Practitioners
7.1.1 Parts and Functionality
7.1.2 User Input: Setting Design Parameters
7.1.3 User Output: Power-Performance-Area Reports
7.1.4 Router Architecture
7.1.5 Power Model of Interconnects Using Data-Flow Matrices
7.2 Implementation
7.2.1 NoC Simulator in C++/SystemC
7.2.2 Router in VHDL
7.2.3 Power Models in C++/Python
7.3 Evaluation
7.3.1 Simulation Performance
7.3.2 Power, Performance, and Area of the RTL Router Model
7.4 Case Study: Link Power Estimation and Optimization
7.5 Conclusion
Part IV 3D-Interconnect Optimization
8 Low-Power Technique for 3D Interconnects
8.1 Fundamental Idea
8.2 Power-Optimal TSV Assignment
8.3 Systematic Net-to-TSV Assignments
8.4 Combination with Traditional Low-Power Codes
8.5 Evaluation
8.5.1 Worst-Case Impact on the 3D-Interconnect Parasitics
8.5.2 Systematic Versus Optimal Assignment for Real Data
8.5.2.1 Image-Sensor Data
8.5.2.2 Smartphone Sensor Data
8.5.3 Combination with Traditional Coding Techniques
8.6 Conclusion
9 Low-Power Technique for High-Performance 3D Interconnects
9.1 Edge-Effect-Aware Crosstalk Classification
9.2 Existing Approaches and Their Limitations
9.3 Proposed Technique
9.3.1 General TSV-CAC Approach
9.3.2 3D-CAC Technique
9.3.2.1 Performance-Optimal 2D-CAC-to-3D-CAC Assignment
9.4 Extension to a Low-Power 3D CAC
9.5 Evaluation
9.5.1 TSV-Performance Improvement
9.5.2 Simultaneous TSV Delay and Power-Consumption Reduction
9.5.3 Comparison with Existing 3D CACs
9.6 Conclusion
10 Low-Power Technique for High-Performance 3D Interconnects in the Presence of Temporal Misalignment
10.1 Temporal-Misalignment Effect on the Crosstalk
10.1.1 Linear Model
10.1.2 Look-Up-Table Model
10.2 Exploiting Misalignment to Improve the Performance
10.3 Effect on the TSV Power Consumption
10.4 Evaluation
10.4.1 Expected Delay Reduction
10.4.2 Delay Reduction for Various Misalignment Scenarios
10.4.3 Comparison with 3D-CAC Techniques
10.5 Conclusion
11 Low-Power Technique for Yield-Enhanced 3D Interconnects
11.1 Existing tsv Yield-Enhancement Techniques
11.2 Preliminaries—Logical Impact of tsv Faults
11.3 Fundamental Idea
11.4 Formal Problem Description
11.4.1 Decodability
11.4.2 Circuit Complexity
11.5 TSV Redundancy Schemes
11.5.1 Fixed-Decoding Scheme
11.5.1.1 Defect Fixing
11.5.1.2 Low-Power Configuration
11.5.2 Fixed-Encoding Scheme
11.6 Evaluation
11.6.1 Yield Enhancement
11.6.1.1 Repair Limitations
11.6.1.2 Overall TSV Yield
11.6.2 Impact on the Power Consumption
11.6.3 Hardware Complexity
11.6.3.1 NVM Cells and Controller
11.6.3.2 Redundancy Scheme
11.7 Case Study
11.8 Conclusion
Part V NoC Optimization for Heterogeneous 3D Integration
12 Heterogeneous Buffering for 3D NoCs
12.1 Buffer Distributions and Depths
12.2 Routers with Optimized Buffer Distribution
12.2.1 Router Pipelines
12.3 Routers with Optimized Buffer Depths
12.4 Evaluation
12.4.1 Routers with Optimized Buffer Distribution
12.4.1.1 Power Savings
12.4.1.2 Area Savings
12.4.1.3 Performance Implications
12.4.2 Routers with Optimized Buffer Depths
12.4.3 Combination of Both Optimizations
12.4.4 Influence of Clock Frequency Deviation
12.5 Discussion
12.6 Conclusion
13 Heterogeneous Routing for 3D NoCs
13.1 Heterogeneity and Routing
13.2 Modeling Heterogeneous Technologies
13.2.1 Area
13.2.1.1 Area of Routers and PEs
13.2.1.2 Router Count
13.2.2 Timing
13.2.2.1 Clock Period
13.3 Modeling Communication
13.3.1 Horizontal Communication
13.3.2 Vertical Communication
13.4 Routing Limitations from Heterogeneity
13.4.1 Tackling Latency with Routing Algorithms
13.4.2 Tackling Throughput with Router Architectures
13.5 Heterogeneous Routing Algorithms
13.5.1 Fundamentals of Heterogeneous Routing Algorithms
13.5.2 Model of the NoC
13.5.2.1 Network Addresses
13.5.2.2 Cardinal Directions
13.5.3 Z+(XY)Z- Routing Algorithm
13.5.4 Proof of Deadlock and Livelock Freedom
13.5.5 Z+(XY)Z-: R1 is Deadlock Free
13.5.6 Livelock Freedom
13.6 Heterogeneous Router Architectures
13.6.1 High Vertical-Throughput Router
13.6.2 Pseudo-Mesochronous High-Throughput Link
13.6.2.1 Implementation for Modern/Future TSV Technologies
13.6.2.2 Implementation for Conservative TSV Technology
13.7 Low-Power Routing in Heterogeneous 3D ICs
13.8 Evaluation
13.8.1 Model Accuracy
13.8.2 Latency of Routing Algorithm Z+(XY)Z-
13.8.3 Throughput of High Vertical-Throughput Router
13.8.4 Area Costs
13.8.5 Power Savings
13.8.6 Case Study
13.9 Discussion
13.9.1 Model Accuracy
13.9.2 Power-Performance-Area Evaluation of Heterogeneous Routing
13.10 Conclusion
14 Heterogeneous Virtualisation for 3D NoCs
14.1 Problem Description
14.2 Heterogeneous Microarchitectures Exploiting Traffic Imbalance
14.3 Evaluation
14.3.1 Area and Energy Consumption
14.3.2 Network Performance
14.3.2.1 Case Study
14.4 Conclusion
15 Network Synthesis and SoC Floor Planning
15.1 Fundamental Idea
15.1.1 Existing Approaches
15.2 Modelling and Optimization
15.2.1 Router Model
15.2.2 Three-Dimensional Technology Model
15.2.3 Modelling Assumptions
15.3 Mixed-Integer Linear Program
15.3.1 Constants and Definitions
15.3.1.1 Component and Communication Model
15.3.1.2 Technologies and Layers Model
15.3.1.3 Implementation Costs Model
15.3.1.4 Energy Model
15.3.1.5 Performance Model
15.3.1.6 Coordinates
15.3.2 Variables
15.3.3 Objective Function
15.3.4 Constraints
15.3.4.1 Network Model
15.3.4.2 Modeling Tiles (Bounding Boxes)
15.3.4.3 Modeling Unequal Positions on SoCs
15.3.4.4 Linearization of Area Products
15.3.4.5 Modeling Routing Algorithms
15.3.5 Case Study: Modeling Elevator-First Dimension-Order Routing
15.4 Heuristic Solution
15.4.1 Heuristic Algorithm
15.5 Evaluation
15.5.1 Performance and Computational Complexity
15.5.2 Mixed-Interger Linear Program
15.5.3 Heuristic Algorithm
15.5.4 Optimization Results
15.5.4.1 Case Study for Technology Model
15.5.4.2 Comparison to Existing Approaches
15.5.4.3 Comparison to the Global Minimum
15.5.4.4 Case Study: Homogeneous 3D SoC
15.5.4.5 Case Study: 3D VSoC
15.5.5 Discussion
15.5.5.1 Comparison to Existing Approaches
15.5.5.2 Step 2 and 5: Placement of Components
15.5.5.3 Step 4: Placement of Vertical Links
15.5.5.4 Validity and Quality of the Results
15.5.5.5 Comparison to Optimal Results
15.5.5.6 Case Study: Homogeneous 3D SoC
15.5.6 Case Study: 3D VSoC
15.5.6.1 Performance of the Heuristic Algorithm
15.5.6.2 Gap to the Optimial Solution
15.6 Conclusion
Part VI Finale
16 Conclusion
16.1 Modeling and Optimization of 3d Interconnects
16.2 Modeling and Optimization of 3d noc
16.3 System Design
16.4 Putting It All Together
16.5 Impact on Future Work
A Pseudo Codes
B Method to Calculate the Depletion-Region Widths
C Modeling Logical OR Relations
References