Z80 CPU User Manual

✍ Scribed by coll.

• Publisher: Zilog, Inc
• Year: 2016
• Tongue: English
• Leaves: 332
• Category: Library

✦ Table of Contents

Z80 CPU User Manual
Revision History
Table of Contents
List of Figures
List of Tables
Architectural Overview
CPU Register
Special-Purpose Registers
General Purpose Registers
Arithmetic Logic Unit
Instruction Register and CPU Control
Pin Functions
Timing
Instruction Fetch
Memory Read Or Write
Input or Output Cycles
Bus Request/Acknowledge Cycle
Interrupt Request/Acknowledge Cycle
Nonmaskable Interrupt Response
HALT Exit
Power-Down Acknowledge Cycle
Power-Down Release Cycle
Interrupt Response
Interrupt Enable/Disable
CPU Response
Hardware and Software Implementation
Minimum System Hardware
Adding RAM
Memory Speed Control
Interfacing Dynamic Memories
Software Implementation Examples
Specific Z80 Instruction Examples
Programming Task Examples
Z80 CPU Instructions
Instruction Types
Addressing Modes
Immediate Addressing
Immediate Extended Addressing
Modified Page Zero Addressing
Relative Addressing
Extended Addressing
Indexed Addressing
Register Addressing
Implied Addressing
Register Indirect Addressing
Bit Addressing
Addressing Mode Combinations
Instruction Notation Summary
Instruction Op Codes
Load and Exchange
Block Transfer and Search
Arithmetic and Logical
Rotate and Shift
Bit Manipulation
Jump, Call, and Return
Input/Output
CPU Control Group
Z80 Instruction Set
Z80 Assembly Language
Z80 Status Indicator Flags
Carry Flag
Add/Subtract Flag
Decimal Adjust Accumulator Flag
Parity/Overflow Flag
Half Carry Flag
Zero Flag
Sign Flag
Z80 Instruction Description
8-Bit Load Group
LD r, r'
LD r,n
LD r, (HL)
LD r, (IX+d)
LD r, (IY+d)
LD (HL), r
LD (IX+d), r
LD (IY+d), r
LD (HL), n
LD (IX+d), n
LD (IY+d), n
LD A, (BC)
LD A, (DE)
LD A, (nn)
LD (BC), A
LD (DE), A
LD (nn), A
LD A, I
LD A, R
LD I,A
LD R, A
16-Bit Load Group
LD dd, nn
LD IX, nn
LD IY, nn
LD HL, (nn)
LD dd, (nn)
LD IX, (nn)
LD IY, (nn)
LD (nn), HL
LD (nn), dd
LD (nn), IX
LD (nn), IY
LD SP, HL
LD SP, IX
LD SP, IY
PUSH qq
PUSH IX
PUSH IY
POP qq
POP IX
POP IY
Exchange, Block Transfer, and Search Group
EX DE, HL
EX AF, AF′
EXX
EX (SP), HL
EX (SP), IX
EX (SP), IY
LDI
LDIR
LDD
LDDR
CPI
CPIR
CPD
CPDR
8-Bit Arithmetic Group
ADD A, r
ADD A, n
ADD A, (HL)
ADD A, (IX + d)
ADD A, (IY + d)
ADC A, s
SUB s
SBC A, s
AND s
OR s
XOR s
CP s
INC r
INC (HL)
INC (IX+d)
INC (IY+d)
DEC m
General-Purpose Arithmetic and CPU Control Groups
DAA
CPL
NEG
CCF
SCF
NOP
HALT
DI
EI
IM 0
IM 1
IM 2
16-Bit Arithmetic Group
ADD HL, ss
ADC HL, ss
SBC HL, ss
ADD IX, pp
ADD IY, rr
INC ss
INC IX
INC IY
DEC ss
DEC IX
DEC IY
Rotate and Shift Group
RLCA
RLA
RRCA
RRA
RLC r
RLC (HL)
RLC (IX+d)
RLC (IY+d)
RL m
RRC m
RR m
SLA m
SRA m
SRL m
RLD
RRD
Bit Set, Reset, and Test Group
BIT b, r
BIT b, (HL)
BIT b, (IX+d)
BIT b, (IY+d)
SET b, r
SET b, (HL)
SET b, (IX+d)
SET b, (IY+d)
RES b, m
Jump Group
JP nn
JP cc, nn
JR e
JR C, e
JR NC, e
JR Z, e
JR NZ, e
JP (HL)
JP (IX)
JP (IY)
DJNZ, e
Call and Return Group
CALL nn
CALL cc, nn
RET
RET cc
RETI
RETN
RST p
Input and Output Group
IN A, (n)
IN r (C)
INI
INIR
IND
INDR
OUT (n), A
OUT (C), r
OUTI
OTIR
OUTD
OTDR
Customer Support