1 Introduction
2 Commodity Hardware Today
2.1 RAM Types
2.1.1 Static RAM
2.1.2 Dynamic RAM
2.1.3 DRAM Access
2.1.4 Conclusions
2.2 DRAM Access Technical Details
2.2.1 Read Access Protocol
2.2.2 Precharge and Activation
2.2.3 Recharging
2.2.4 Memory Types
2.2.5 Conclusions
2.3 Other Main Memory Users
3 CPU Caches
3.1 CPU Caches in the Big Picture
3.2 Cache Operation at High Level
3.3 CPU Cache Implementation Details
3.3.1 Associativity
3.3.2 Measurements of Cache Effects
3.3.3 Write Behavior
3.3.4 Multi-Processor Support
3.3.5 Other Details
3.4 Instruction Cache
3.4.1 Self Modifying Code
3.5 Cache Miss Factors
3.5.1 Cache and Memory Bandwidth
3.5.2 Critical Word Load
3.5.3 Cache Placement
3.5.4 FSB Influence
4 Virtual Memory
4.1 Simplest Address Translation
4.2 Multi-Level Page Tables
4.3 Optimizing Page Table Access
4.3.1 Caveats Of Using A TLB
4.3.2 Influencing TLB Performance
4.4 Impact Of Virtualization
5 NUMA Support
5.1 NUMA Hardware
5.2 OS Support for NUMA
5.3 Published Information
5.4 Remote Access Costs
6 What Programmers Can Do
6.1 Bypassing the Cache
6.2 Cache Access
6.2.1 Optimizing Level 1 Data Cache Access
6.2.2 Optimizing Level 1 Instruction Cache Access
6.2.3 Optimizing Level 2 and Higher Cache Access
6.2.4 Optimizing TLB Usage
6.3 Prefetching
6.3.1 Hardware Prefetching
6.3.2 Software Prefetching
6.3.3 Special Kind of Prefetch: Speculation
6.3.4 Helper Threads
6.3.5 Direct Cache Access
6.4 Multi-Thread Optimizations
6.4.1 Concurrency Optimizations
6.4.2 Atomicity Optimizations
6.4.3 Bandwidth Considerations
6.5 NUMA Programming
6.5.1 Memory Policy
6.5.2 Specifying Policies
6.5.3 Swapping and Policies
6.5.4 VMA Policy
6.5.5 Querying Node Information
6.5.6 CPU and Node Sets
6.5.7 Explicit NUMA Optimizations
6.5.8 Utilizing All Bandwidth
7 Memory Performance Tools
7.1 Memory Operation Profiling
7.2 Simulating CPU Caches
7.3 Measuring Memory Usage
7.4 Improving Branch Prediction
7.5 Page Fault Optimization
8 Upcoming Technology
8.1 The Problem with Atomic Operations
8.2 Transactional Memory
8.2.1 Load Lock/Store Conditional Implementation
8.2.2 Transactional Memory Operations
8.2.3 Example Code Using Transactional Memory
8.2.4 Bus Protocol for Transactional Memory
8.2.5 Other Considerations
8.3 Increasing Latency
8.4 Vector Operations
A Examples and Benchmark Programs
A.1 Matrix Multiplication
A.2 Debug Branch Prediction
A.3 Measure Cache Line Sharing Overhead
B Some OProfile Tips
B.1 Oprofile Basics
B.2 How It Looks Like
B.3 Starting To Profile
C Memory Types
D libNUMA Introduction
E Index
F Bibliography
G Revision History