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VLSI simulation device


Publisher
Elsevier Science
Year
1986
Tongue
English
Weight
114 KB
Volume
9
Category
Article
ISSN
0140-3664

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๐Ÿ“œ SIMILAR VOLUMES


VLSI architecture for device simulation
โœ Cheng T. Wang ๐Ÿ“‚ Article ๐Ÿ“… 1986 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 756 KB

In this paper, VLSI architectures for solving nonlinear equations are presented, such as the elliptic partial differential equations arising from semiconductor device modeling using a Newton-SOR (Successive Over Relaxation), finite difference, iterative scheme. The computation time for the matrix in

A sputter equipment simulation system fo
โœ T Ohta; H Yamada ๐Ÿ“‚ Article ๐Ÿ“… 1998 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 650 KB

In order to optimize the sputter deposition process to fill a minute VLSI's contact hole efficiently, we have developed a practical sputter equipment simulation system named ''SimDepo''. The system is composed of (1) the trajectory calculation of sputtered particles using the Monte Carlo method taki

Simulation software for VLSI
๐Ÿ“‚ Article ๐Ÿ“… 1983 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 114 KB
Efficient VLSI fault simulation
โœ John H. Reif ๐Ÿ“‚ Article ๐Ÿ“… 1993 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 925 KB

Let C be an acycfic Boolean circuit with n gates and \_< n inputs. A circuit manufacture error may result in a "Stuck-at" (S-A) fault in a circuit identical to C except a gate v only outputs a fixed Boolean value. The S-A fault simulation problem for C is to determine all possible (S-A) faults which