VLSI Risc Architecture and Organization (Electrical and Computer Engineering)

✍ Scribed by Stephen B. Furber

• Publisher: Routledge
• Year: 1989
• Tongue: English
• Leaves: 392
• Edition: 1
• Category: Library

✦ Synopsis

With the expectation that architectural improvements will play a significant role in advancing processor performance, it is critical for readers to maintain an up-to-date, unified overview of technological advances in this vital research area. Gathering into one place material that had been scattered throughout the literature making it difficult to obtain detailed information on computer designs-this important book describes the main architectural and organizational features of modem mini- and microcomputers. In addition, it explains the RISC philosophy by supplying historical background information and excellent examples of several commercially available RISC microprocessors. Limiting attention to VLSI implementations of RISC processors, VLSI RISC Architecture and Organization offers insight into design issues that arose in developing a RISC system, using the VLSI RISC chip set developed at Acorn Computers Limited as an example ... discusses options considered during the design process, the basis for the decisions made, and implementation details . . . describes contemporary RISC architecture, comparing and contrasting different designs ... and looks at future trends in RISC research. Discussing the topic cohesively and comprehensively - from initial study into reduced instructions sets to the widespread introduction of RISC architectures into mainstream computer products - VLSI RISC Architecture and Organization is an invaluable reference for electrical, electronics, and computer engineers; computer architects and scientists; hardware systems designers; and upper-level undergraduate and graduate students in computer science and electrical engineering courses.

✦ Table of Contents

Cover
Title Page
Copyright Page
Contents
Preface
1. THE EVOLUTION OF COMPUTER ARCHITECTURE
1.1 Basic Computer Architecture
1.1.1 The von Neumann Architecture
1.1.2 The Harvard Architecture
1.1.3 The Central Processing Unit
1.1.4 The Memory System
1.1.5 The Input/Output System
1.2 Advancing Technologies
1.2.1 Logic Technologies
1.2.2 Memory Technologies
1.2.3 The Impact of VLSI
1.3 Architectural Advances
1.3.1 Powerful Instruction Sets & Microcode
1.3.2 Virtual Memory
1.3.3 Multi-tasking
1.3.4 Cache Memory
1.3.5 Hardware Accelerators
1.3.6 Parallel Processing
1.4 Software Considerations
1.4.1 Operating Systems
1.4.2 High-Level Languages
1.5 The Design Process
1.5.1 Levels of Knowledge
1.5.2 Balanced Systems
1.5.3 Market Success
1.6 The VAX-11/780
1.6.1 Architecture
1.6.2 Organization and Implementation
1.7 The Reduced Instruction Set Computer
1.7.1 Concluding Remarks
References
2. RESEARCH INTO REDUCED INSTRUCTION SETS
2.1 The IBM 801
2.1.1 The 801 Design Philosophy
2.1.2 Instruction Set
2.1.3 Organization
2.1.4 Historical Perspective
2.2 The Berkeley RISC Architecture
2.2.1 The Background to the Berkeley RISC Project
2.2.2 The Berkeley RISC II Programmer's Model
2.2.3 The Berkeley RISC Instruction Set
2.2.4 Operation of the RISC II Register Windows
2.2.5 The Implementation of RISC II
2.2.6 A VLSI Cache for RISC II
2.3 Stanford MIPS
2.3.1 The MIPS Instruction Set
2.3.2 The Implementation of MIPS
2.3.3 MIPS Software Issues
2.4 Conclusions
References
3. COMMERCIAL VLSI RISC
3.1 The IBM 6150 RT PC
3.1.1 ROMP Architecture
3.1.2 ROMP Organization
3.1.3 Conclusions
3.2 The VL86C010 Acorn RISC Machine
3.2.1 Architecture
3.2.2 Organization
3.2.3 The Memory Controller
3.2.4 Conclusions
3.3 The Sun SPARC
3.3.1 Instruction Set
3.3.2 Architecture
3.3.3 Implementation
3.3.4 Conclusions
3.4 The MIPS R2000
3.4.1 The R2000 Architecture
3.4.2 The System Control Coprocessor
3.4.3 Organization
3.4.4 The R2010 Floating-Point Coprocessor
3.4.5 R2000 Cache Organization
3.4.6 Conclusions
3.5 The AT&T CRISP
3.5.1 Instruction Set
3.5.2 Architecture
3.5.3 Conclusions
3.6 The Am29000
3.6.1 Instruction Set
3.6.2 Organization
3.6.3 Conclusions
3.7 The HP Precision Architecture
3.7.1 System Organization
3.7.2 Architecture
3.7.3 Organization
3.7.4 Conclusions
3.8 The Motorola M88000
3.8.1 Architecture
3.8.2 Organization
3.8.3 Conclusions
3.9 The Intel 80960KB
3.9.1 Architecture
3.9.2 Organization
3.9.3 Conclusions
3.10 The Intergraph CLIPPER
3.10.1 Architecture
3.10.2 Organization
3.10.3 Conclusions
3.11 The Inmos T800 Transputer
3.11.1 Architecture
3.11.2 Organization
3.11.3 Conclusions
References
4. THE IMPLEMENTATION OF THE ARM
4.1 Instruction Set and Datapath Definition
4.1.1 The Condition Field
4.1.2 Branch and Branch with Link Instructions
4.1.3 Data Processing Instructions
4.1.4 Single Register Load and Store Instructions
4.1.5 Block Data Transfer Instructions
4.1.6 Software Interrupt Instruction
4.1.7 Multiply and Multiply-Accumulate Instructions
4.1.8 Coprocessor Data Operation Instructions
4.1.9 Coprocessor Data Transfer Instructions
4.1.10 Coprocessor Register Transfer Instructions
4.1.11 Undefined Instructions and Coprocessor Absent
4.1.12 Unexecuted Instructions
4.2 Instruction Set Examples
4.3 Instruction Speeds
4.4 Instruction Usage
4.5 Design Methodology
4.6 Datapath Implementation
4.7 Control Logic Implementation
4.8 Timing Characteristics
4.9 The Memory Interface
4.9.1 Cycle Types
4.10 The Coprocessor Interface
4.11 Concluding Remarks
References
5. FURTHER RISC RESEARCH
5.1 The Berkeley SPUR Project
5.1.1 Architecture
5.1.2 Organization
5.1.3 Conclusions
5.2 MIPS-X
5.2.1 Architecture
5.2.2 Organization
5.2.3 Conclusions
5.3 ARM3-an ARM CPU with Cache
5.3.1 Cache Organization
5.3.2 Cache Control Registers
5.3.3 Chip Organization
5.3.4 Cache Implementation
5.3.5 Testability
5.3.6 An ARM3 System
5.3.7 Concluding Remarks
5.4 Analysing Architectural Decisions
5.5 The Limits to Performance
5.5.1 Power Dissipation
5.5.2 The Floating-Point Unit
5.5.3 The Future of RISC
References
Acronyms
Index