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VLSI circuit for programmable sorting

โœ Scribed by Fabio Ancona; Stefano Rovetta; Rodolfo Zunino


Book ID
114288643
Publisher
Elsevier Science
Year
1999
Tongue
English
Weight
79 KB
Volume
20
Category
Article
ISSN
0920-5489

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State-of-the-art technologies for VLSI circuits give rise to various defect mechanisms that may cause a circuit to fail when operated at its designated speed of operation. Such defects are conventionally modeled by delay faults. In this paper, we review delay fault models used for circuits described