VHDL : programming by example

✍ Scribed by Perry, Douglas L

Publisher: McGraw-Hill
Year: 2002
Tongue: English
Leaves: 476
Edition: 4th ed
Category: Library

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✦ Synopsis

THE HANDS-DOWN FAVORITE USER’S GUIDE TO VHDLCOMPLETELY UPDATED TO REFLECT THE VERY LATEST DESIGN METHODS

CD-ROM WITH WORKING CODE EXAMPLES, VERIFICATION TOOLS AND MORE

No matter what your current level of expertise, nothing will have you writing and verifying concise, efficient VHDL descriptions of hardware designs as fast – or as painlessly – as this classic tutorial from master teacher Doug Perry. Beginners will find it an invaluable learning tool and experienced pros will keep it on their desk as a trusted reference.

Perry teaches VHDL through a series of hundreds of practical, detailed examples, gradually increasing in complexity until you’re capable of designing a fully functional CPU. The new Fourth Edition has been completely updated with all of the VDHL codes used in the examples changed to reflect today’s faster and more efficient design methods. You’ll also find:
A CD-ROM containing working code of all of the VDHL examples, with their matching designs along with VITAL verification tools and a working copy of ModelSIM
All the tools you need for simulation and synthesis
A listing of the IEEE 1164 STD-LOGIC package used throughout the book
Useful tables and figures
* Instructions for reading the Bachus-Naur format (BNF) descriptions found in the VHDL Language Reference Manual

There truly is no faster or smarter way to master VHDL than Doug Perry’s “learn by example” approach. It works!

✦ Table of Contents

Content: Ch. 1. Introduction to VHDL --
Ch. 2. Behavioral Modeling --
Ch. 3. Sequential Processing --
Ch. 4. Data Types --
Ch. 5. Subprograms and Packages --
Ch. 6. Predefined Attributes --
Ch. 7. Configurations --
Ch. 8. Advanced Topics --
Ch. 9. Synthesis --
Ch. 10. VHDL Synthesis --
Ch. 11. High Level Design Flow --
Ch. 12. Top-Level System Design --
Ch. 13. CPU: Synthesis Description --
Ch. 14. CPU: RTL Simulation --
Ch. 15. CPU Design: Synthesis Results --
Ch. 16. Place and Route --
Ch. 17. CPU: VITAL Simulation --
Ch. 18. At Speed Debugging Techniques --
App. A. Standard Logic Package --
App. B. VHDL Reference Tables --
App. C. Reading VHDL BNF --
App. D. VHDL93 Updates.

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