VHDL 101 is written for Electrical Engineers and others wishing to break into FPGA design and assumes a basic knowledge of digital design and some experience with engineering 'process'. Bill Kafig, industry expert, swiftly brings the reader up to speed on techniques and functions commonly used in VH
VHDL 101: Everything you need to know to get started
✍ Scribed by William Kafig
- Publisher
- Newnes
- Year
- 2011
- Tongue
- English
- Leaves
- 205
- Category
- Library
No coin nor oath required. For personal study only.
✦ Synopsis
VHDL (VHSIC Hardware Description Language) is a hardware programming language commonly used for FPGA (Field Programable Gate Array) or ASIC (Application Specific Integrated Circuit) designs. FPGAs and the like are often found within larger applications such as cell phones, medical imagers, and personal media devices. As these devices are becoming more ubiquitous so the need for engineers fluent in VHDL design grows. Engineers commonly face an immediate need to learn a language or technique quickly and this book answers that requirement. Bill Kafig of industry leader Xilinx, swiftly brings the reader up to speed on techniques and functions commonly used as well as commands and data management. Extensive simple, complete designs are accompany the content for maximum comprehension. The book concludes with a section on design re-use which is of utmost importance to today's engineer that needs to meet a deadline and lower costs per unit. Gets you up to speed with VHDL fast, reducing time to market and driving down costs FPGA market will be worth $2.75bn in 2010 Coves the basics including language concepts and includes complete design examples for ease of learning Get inside track experience from Kafig, a Xilinx insider *Includes FREE Xilinx Software and ISE Development Tools!
✦ Table of Contents
Front Matter
......Page 1
Copyright
......Page 2
About the Author......Page 3
Preface......Page 4
Other things you should know…......Page 5
Acknowledgments......Page 7
Language Constructs......Page 199
VHDL......Page 8
Brief History of VHDL......Page 9
Coding Styles: Structural vs. Behavioral vs. RTL......Page 10
FPGA Architecture......Page 11
Creating the Design......Page 14
Paper exercise......Page 15
Design Entry......Page 18
Loop 3......Page 26
Synthesis......Page 20
Simulation......Page 21
Map......Page 24
Flexibility Using Generics and Constants......Page 156
Bitstream Generation......Page 25
The Many Levels of Comments......Page 28
Library and Package Inclusion......Page 32
Entity......Page 34
Architecture......Page 35
Configuration Statements......Page 36
Signals......Page 37
The Naming of Names......Page 38
Enumeration types......Page 41
Integer types......Page 43
Physical types......Page 44
Composite types......Page 45
Slices and aggregates......Page 47
Records......Page 50
Operators......Page 54
Details and examples......Page 55
Relational operators (=, /=, <, <=, ﹥, ﹥=)......Page 57
Shifting operators (sll, srl, sla, sra, rol, ror)......Page 58
Mathematical operators: (+, −, , /, mod, rem, &, not, abs, *)......Page 60
Concatenation......Page 62
Casting......Page 63
Conversion functions......Page 64
Concurrent Statements......Page 66
Unconditional assignment (<=)......Page 70
Conditional assignment – when/else......Page 71
Multiple selection conditional assignment (with/select)......Page 73
Conditional assignment – time-based......Page 75
Instantiations, inferences, and hierarchy......Page 76
Instantiation and Inference......Page 80
Transmitter......Page 84
Receiver......Page 85
Introducing the Simulation Environment......Page 90
The unit/device under test......Page 92
Introducing Processes, Variables, and Sequential Statements......Page 98
Variable use......Page 108
Ordering of statements......Page 109
Signals within Processes......Page 112
The synchronous process......Page 117
Resetting processes......Page 118
If/then/elsif/else/end if......Page 120
Case statement......Page 122
Coding the transmitter......Page 130
Coding the Test Bench for the Top-Level UART Design......Page 143
Synthesis Options......Page 146
Constraints......Page 148
Introducing Concept of Reuse......Page 149
A Little More on Libraries and Packages…......Page 150
Resolving conflicts between packages......Page 154
Generics on the other hand…......Page 157
Conditional Generate Form......Page 159
Generate Loop Form......Page 162
Driving the Generics…......Page 167
Functions and Procedures......Page 171
Function and Procedure Parameters......Page 174
Overloading......Page 175
When to Use Procedures and Functions......Page 176
Using Functions and Procedures......Page 178
Attributes......Page 182
Packages......Page 186
Simulation Packages......Page 191
IEEE_1164......Page 192
NUMERIC_STD......Page 193
TEXTIO......Page 195
Standard Libraries......Page 200
Index......Page 202
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