Finite automata and temporal logics have been used extensively to formally verify qualitative properties of concurrent systems. The properties include deadlock-or livelock-freedom, the eventual occurrence of an event, and the satisfaction of a predicate. The need to reason with absolute time is unne
β¦ LIBER β¦
Verification of Asynchronous Circuits using Timed Automata
β Scribed by Marius Bozga; Hou Jianmin; Oded Maler; Sergio Yovine
- Publisher
- Elsevier Science
- Year
- 2002
- Tongue
- English
- Weight
- 162 KB
- Volume
- 65
- Category
- Article
- ISSN
- 1571-0661
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
Real-Time Systems || Verification Using
β
Cheng, Albert M. K.
π
Article
π
2002
π
John Wiley & Sons, Inc.
β 192 KB
π 2 views
Presburger liveness verification of disc
β
Zhe Dang; Pierluigi San Pietro; Richard A. Kemmerer
π
Article
π
2003
π
Elsevier Science
π
English
β 259 KB
Using an automata-theoretic approach, we investigate the decidability of liveness properties (called Presburger liveness properties) for timed automata when Presburger formulas on conΓΏgurations are allowed. While the general problem of checking a temporal logic such as TPTL augmented with Presburger
Verification of asynchronous circuits ba
β
Koichi Masukura; Minoru Tomisaka; Tomohiro Yoneda
π
Article
π
2001
π
John Wiley and Sons
π
English
β 380 KB
Runtime Verification of Timed LTL using
β
KΓ₯re Jelling Kristoffersen; Christian Pedersen; Henrik Reif Andersen
π
Article
π
2003
π
Elsevier Science
π
English
β 805 KB
A note on the verification of automata s
β
Arnaldo V. Moura; Guilherme A. Pinto
π
Article
π
2002
π
Elsevier Science
π
English
β 95 KB
Simulation study of switched circuit com
β
M.S. Chrystall; P. Mars
π
Article
π
1982
π
Elsevier Science
π
English
β 650 KB