Verification and Validation in Systems Engineering: Assessing UML/SysML Design Models
β Scribed by Mourad Debbabi, Fawzi HassaΓ―ne, Yosr Jarraya, Andrei Soeanu, Luay Alawneh (auth.)
- Publisher
- Springer-Verlag Berlin Heidelberg
- Year
- 2010
- Tongue
- English
- Leaves
- 267
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
β¦ Synopsis
Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle.
Debbabi and his coauthors investigate methodologies and techniques that can be employed for the automatic verification and validation of systems engineering design models expressed in standardized modeling languages. Their presentation includes a birdβs eye view of the most prominent modeling languages for software and systems engineering, namely the Unified Modeling Language (UML) and the more recent Systems Modeling Language (SysML). Moreover, it elaborates on a number of quantitative and qualitative techniques that synergistically combine automatic verification techniques, program analysis, and software engineering quantitative methods applicable to design models described in these modeling languages. Each of these techniques is additionally explained using a case study highlighting the process, its results, and resulting changes in the system design.
Researchers in academia and industry as well as students specializing in software and systems engineering will find here an overview of state-of-the-art validation and verification techniques. Due to their close association with the UML standard, the presented approaches are also applicable to industrial software development.
β¦ Table of Contents
Front Matter....Pages i-xxvi
Introduction....Pages 1-13
Architecture Frameworks, Model-Driven Architecture, and Simulation....Pages 15-35
Unified Modeling Language....Pages 37-59
Systems Modeling Language....Pages 61-73
Verification, Validation, and Accreditation....Pages 75-93
Automatic Approach for Synergistic Verification and Validation....Pages 95-105
Software Engineering Metrics in the Context of Systems Engineering....Pages 107-124
Verification and Validation of UML Behavioral Diagrams....Pages 125-152
Probabilistic Model Checking of SysML Activity Diagrams....Pages 153-166
Performance Analysis of Time-Constrained SysML Activity Diagrams....Pages 167-188
Semantic Foundations of SysML Activity Diagrams....Pages 189-203
Soundness of the Translation Algorithm....Pages 205-222
Conclusion....Pages 223-226
Back Matter....Pages 227-248
β¦ Subjects
Software Engineering; System Performance and Evaluation; Management of Computing and Information Systems
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