Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors-chip design and system implementation

✍ Scribed by Kuznia, C.B.; Wu, J.-M.; Chen, C.-H.; Hoanca, B.; Cheng, L.; Weber, A.G.; Sawchuk, A.A.

• Book ID: 117866274
• Publisher: IEEE
• Year: 1999
• Tongue: English
• Weight: 671 KB
• Volume: 5
• Category: Article
• ISSN: 1077-260X
• DOI: 10.1109/2944.778326