Transistor channel lengths are being continually scaled to smaller dimensions to improve the high-frequency performance and package density, which will lead to the introduction of sub-50 nm gate lengths in production in the near future. In this paper, the performance of a double gate (DG) vertical m
Top contacts for vertical double-gate MOSFETs
✍ Scribed by J Moers; St Trellenkamp; M Goryll; M Marso; A van der Hart; S Hogg; S Mantl; P Kordoš; H Lüth
- Book ID
- 104305763
- Publisher
- Elsevier Science
- Year
- 2002
- Tongue
- English
- Weight
- 398 KB
- Volume
- 64
- Category
- Article
- ISSN
- 0167-9317
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✦ Synopsis
As scaling of electronic devices goes on, the issue of short channel effects draws growing attention. Double-gate MOSFETs are known to reduce short channel behaviour effectively [Proc. IEEE 85 (1997) 486] and therefore have gained increasing attention for future CMOS application. Here a vertical layout is discussed, where the current flow is perpendicular to the surface. In an already realised layout [Proc. ESSDERC (2001) 191] the device performance is ruled by the resistance of the top contact. In a revised layout the top contact is implemented directly on top of the transistor. Here the layout and the technology steps to obtain this structure are discussed.
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