Methods are presented for designing threshold gate networks with error-correcting capabilities. The particular method presented is an extension of the tree method for realizing a Boolean junction. A primary realization is a realization for some junction on the tree such that either the separating j
β¦ LIBER β¦
Threshold logic network synthesis with specific threshold-gate sensitivities
β Scribed by Hurst, S.L.
- Book ID
- 119749095
- Publisher
- Institution of Electrical Engineers
- Year
- 1972
- Weight
- 627 KB
- Volume
- 42
- Category
- Article
- ISSN
- 0033-7722
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We present simulation mechanisms by which any network of threshold logic units with either symmetric or asymmetric interunit connections (i.e. a symmetric or asymmetric "Hopfield net") can be simulated on a network of the same type, but without any a priori constraints on the order of updates of the