No coin nor oath required. For personal study only.
With increasing complexity of VLSI systems, hardware testability structures are becoming more commonplace. While such structures were ad-hoc in the past, an increasing emphasis is being placed on their automatic synthesis. This workshop, the third in the series, has been proposed to discuss all aspects of Test Synthesis, loosely defined as the enabling technology of Design-for-Test. The topics include, but are not limited to, the following: * High-Level/Behavioral Test Synthesis * Technology-independent test synthesis * Test Synthesis for Mixed Signal Circuits * Economics of test synthesis * Tools to support test synthesis * Test synthesis for IDDQ testing * Synthesis of Testable Sequential Circuits * Design For Testability * Scan Optimization * DfT Rule Checking * Test Pattern Generation * Synthesis for BIST * Diagnostic test synthesis * Synthesis of Testable Combinational Circuits * Test synthesis for programmable structures * Relating test-synthesis to logic or behavioral-level optimization Participation:
To maintain the focused format of the workshop, participation will be limited to 70 attendees. Please register your interest by completing and returning the attached Workshop
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