๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout

โœ Scribed by Chow, P.; Soon Ong Seo, ; Rose, J.; Chung, K.; Paez-Monzon, G.; Rahardja, I.


Book ID
120167379
Publisher
IEEE
Year
1999
Tongue
English
Weight
516 KB
Volume
7
Category
Article
ISSN
1063-8210

No coin nor oath required. For personal study only.


๐Ÿ“œ SIMILAR VOLUMES


Design of a field programmable gate arra
โœ J. Carletta; G. Giakos; N. Patnekar; L. Fraiwan; F. Krach ๐Ÿ“‚ Article ๐Ÿ“… 2004 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 324 KB

In this study, the design of a low-cost, field programmable gate array (FPGA)-based digital hardware platform that implements wavelet transform algorithms for real-time signal de-noising of optical imaging signals is presented. The proposed digital hardware de-noising platform can achieve a throughp