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The design of a block-regularized parameter estimator by algorithmic engineering

✍ Scribed by D. W. Brown; J. G. McWhirter

Publisher: John Wiley and Sons
Year: 1997
Tongue: English
Weight: 233 KB
Volume: 11
Category: Article
ISSN: 0890-6327
DOI: 10.1002/(sici)1099-1115(199708)11:5<381::aid-acs414>3.0.co;2-x

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✦ Synopsis

Hierarchical signal flow graphs (HSFGs) are used to illustrate the computations and data flow required for the block-regularized parameter estimation algorithm. Block regularization protects the underlying recursive least squares (RLS) parameter estimation from numerical difficulties which can occur if the input data are not persistently exciting or the behaviour of the underlying model is unknown. Hierarchical signal flow graphs provide a very concise representation of the algorithm and a relatively simple approach to the design of efficient parallel architectures. The design of a two-dimensional systolic array is demonstrated in the paper.

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