The Definitive Guide to the ARM Cortex-M3

✍ Scribed by Joseph Yiu

• Publisher: Newnes
• Year: 2007
• Tongue: English
• Leaves: 380
• Series: Embedded Technology
• Category: Library

✦ Synopsis

This user's guide does far more than simply outline the ARM Cortex-M3 CPU features; it explains step-by-step how to program and implement the processor in real-world designs. It teaches readers how to utilize the complete and thumb instruction sets in order to obtain the best functionality, efficiency, and reuseability. The author, an ARM engineer who helped develop the core, provides many examples and diagrams that aid understanding. Quick reference appendices make locating specific details a snap! Whole chapters are dedicated to: Debugging using the new CoreSight technology Migrating effectively from the ARM7 The Memory Protection Unit Interfaces, Exceptions,Interrupts ...and much more! The only available guide to programming and using the groundbreaking ARM Cortex-M3 processor Easy-to-understand examples, diagrams, quick reference appendices, full instruction and Thumb-2 instruction sets are all included *The author, an ARM engineer on the M3 development team, teaches end users how to start from the ground up with the M3, and how to migrate from the ARM7

✦ Table of Contents

Definitive Guide to ARM Cortex-M3......Page 1
Copyright......Page 5
Table of Contents......Page 6
Foreword......Page 14
Preface......Page 15
Acknowledgments......Page 16
Terms & Abbreviations......Page 17
Conventions......Page 19
References......Page 20
What Is the ARM Cortex-M3 Processor?......Page 22
A Brief History......Page 24
Architecture Versions......Page 25
Processor Naming......Page 27
Instruction Set Development......Page 29
The Thumb-2 Instruction Set Architecture (ISA)......Page 30
Cortex-M3 Processor Applications......Page 31
Further Readings......Page 32
Fundamentals......Page 34
R13: Stack Pointers......Page 35
Special Registers......Page 36
Operation Modes......Page 37
The Built-In Nested Vectored Interrupt Controller......Page 38
Interrupt Masking......Page 39
The Memory Map......Page 40
The Instruction Set......Page 41
Interrupts and Exceptions......Page 43
Debugging Support......Page 45
Advanced Interrupt-Handling Features......Page 46
Debug Supports......Page 47
General-Purpose Registers R8–R12......Page 50
Stack Pointer R13......Page 51
Link Register R14......Page 53
Program Status Registers (PSRs)......Page 54
PRIMASK, FAULTMASK, and BASEPRI Registers......Page 56
The Control Register......Page 57
Operation Mode......Page 58
Exceptions and Interrupts......Page 60
Vector Tables......Page 61
Basic Operations of the Stack......Page 62
Cortex-M3 Stack Implementation......Page 63
The Two-Stack Model in the Cortex-M3......Page 64
Reset Sequence......Page 65
Assembler Language: Basic Syntax......Page 68
Assembler Language: Use of Suffi xes......Page 69
Assembler Language: Unifi ed Assembler Language......Page 70
Instruction List......Page 71
Unsupported Instructions......Page 76
Assembler Language: Moving Data......Page 78
LDR and ADR Pseudo Instructions......Page 81
Assembler Language: Processing Data......Page 82
Assembler Language: Call and Unconditional Branch......Page 87
Assembler Language: Decisions and Conditional Branches......Page 88
Assembler Language: Combined Compare and Conditional Branch......Page 91
Assembler Language: Conditional Branches Using IT Instructions......Page 92
Assembler Language: Instruction Barrier and Memory Barrier Instructions......Page 93
Assembly Language: Saturation Operations......Page 94
MSR and MRS......Page 96
IF-THEN......Page 97
CBZ and CBNZ......Page 98
RBIT......Page 99
UBFX and SBFX......Page 100
TBB and TBH......Page 101
Memory Maps......Page 104
Memory Access Attributes......Page 107
Bit-Band Operations......Page 109
Advantages of Bit-Band Operations......Page 113
Bit-Band Operations in C Programs......Page 116
Unaligned Transfers......Page 117
Exclusive Accesses......Page 119
Endian Mode......Page 121
The Pipeline......Page 124
A Detailed Block Diagram......Page 126
The D-Code Bus......Page 129
The External Private Peripheral Bus......Page 130
Typical Connections......Page 132
Reset Signals......Page 133
Exception Types......Page 136
Defi nitions of Priority......Page 138
Vector Tables......Page 144
Interrupt Inputs and Pending Behavior......Page 145
Bus Faults......Page 148
Memory Management Faults......Page 150
Usage Faults......Page 151
Dealing with Faults......Page 153
SVC and PendSV......Page 154
NVIC Overview......Page 158
Interrupt Pending and Clear Pending......Page 159
Priority Levels......Page 161
PRIMASK and FAULTMASK Special Registers......Page 162
The BASEPRI Special Register......Page 163
Confi guration Registers for Other Exceptions......Page 164
Example Procedures in Setting Up an Interrupt......Page 165
Software Interrupts......Page 167
The SYSTICK Timer......Page 168
Stacking......Page 170
Vector Fetches......Page 171
Exception Exits......Page 172
Tail-Chaining Interrupts......Page 173
More on the Exception Return Value......Page 174
Interrupt Latency......Page 175
Stacking......Page 177
Invalid Returns......Page 178
Using Assembly......Page 180
Using C......Page 181
The Interface Between Assembly and C......Page 182
The First Step......Page 183
Producing Outputs......Page 185
The “Hello World” Example......Page 186
Using Data Memory......Page 190
Using Exclusive Access for Semaphores......Page 191
Using Bit-Band for Semaphores......Page 193
Working with Bit Field Extract and Table Branch......Page 194
Stack Setup......Page 196
Vector Table Setup......Page 197
Interrupt Priority Setup......Page 198
Enable the Interrupt......Page 199
Exception/Interrupt Handlers......Page 200
Software Interrupts......Page 201
Example with Exception Handlers......Page 202
Using SVC......Page 205
SVC Example: Use for Output Functions......Page 207
Using SVC with C......Page 210
Running a System with Two Separate Stacks......Page 214
Double-Word Stack Alignment......Page 217
Nonbase Thread Enable......Page 218
Performance Considerations......Page 221
What Happens During Lockup?......Page 222
Avoiding Lockup......Page 223
Overview......Page 226
MPU Registers......Page 227
Setting Up the MPU......Page 232
Example Use of the Subregion Disable......Page 238
The SYSTICK Timer......Page 244
Power Management......Page 248
Multiprocessor Communication......Page 250
Self-Reset Control......Page 252
Debugging Features Overview......Page 254
Processor Debugging Interface......Page 255
DP Module, AP Module, and DAP......Page 256
Trace Interface......Page 257
CoreSight Characteristics......Page 258
Debug Modes......Page 260
Debugging Events......Page 262
Breakpoint in the Cortex-M3......Page 264
Accessing Register Content in Debug......Page 265
Other Core Debugging Features......Page 266
The Trace System in the Cortex-M3......Page 268
Trace Components: Data Watchpoint and Trace......Page 269
Trace Components: Instrumentation Trace Macrocell......Page 271
ITM Timestamp......Page 272
Trace Components: Embedded Trace Macrocell......Page 273
The Flash Patch and Breakpoint Unit......Page 274
The AHB Access Port......Page 277
ROM Table......Page 278
Choosing a Cortex-M3 Product......Page 280
Differences Between Cortex-M3 Revision 0 and Revision 1......Page 281
Revision 1 Change: Moving from JTAG-DP to SWJ-DP......Page 282
C Compiler......Page 283
Embedded Operating System Support......Page 284
Overview......Page 286
Interrupts......Page 287
Operation Modes......Page 288
Thumb State......Page 289
ARM State......Page 290
Optimization......Page 292
Getting the GNU Tool Chain......Page 294
Development Flow......Page 295
Example 1: The First Program......Page 296
Example 2: Linking Multiple Files......Page 298
Example 3: A Simple “Hello World” Program......Page 299
Example 4: Data in RAM......Page 301
Example 5: C Only, Without Assembly File......Page 302
Example 6: C Only, with Standard C Startup Code......Page 306
Inline Assembler in the GNU C Compiler......Page 308
Overview......Page 310
Getting Started with μVision......Page 311
Outputting the “Hello World” Message via UART......Page 316
Testing the Software......Page 319
Using the Debugger......Page 321
The Instruction Set Simulator......Page 324
Modifying the Vector Table......Page 326
Stopwatch Example with Interrupts......Page 327
Supported 16-Bit Thumb Instructions......Page 336
Supported 32-Bit Thumb-2 Instructions......Page 340
AppB 16-Bit Thumb Instructions & Architecture Versions......Page 350
Exception Types and Enables......Page 352
Stack Contents after Exception Stacking......Page 353
AppD NVIC Registers Quick Reference......Page 354
Overview......Page 368
Developing Fault Handlers......Page 369
Report Stacked PC......Page 370
Others......Page 371
Understanding the Cause of the Fault......Page 372
Other Possible Problems......Page 375
Index......Page 376