✦ LIBER ✦
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs
✍ Scribed by Bahukudumbi, S.; Chakrabarty, K.
- Book ID
- 117908044
- Publisher
- IEEE
- Year
- 2009
- Tongue
- English
- Weight
- 438 KB
- Volume
- 28
- Category
- Article
- ISSN
- 0278-0070
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