Systolic array implementation of artificial neural networks
β Scribed by K Vijayan Asari; C Eswaran
- Publisher
- Elsevier Science
- Year
- 1994
- Tongue
- English
- Weight
- 601 KB
- Volume
- 18
- Category
- Article
- ISSN
- 0141-9331
No coin nor oath required. For personal study only.
π SIMILAR VOLUMES
This paper presents a mapping scheme for the proposed implementation of neural network models on systolic arrays. The mapping technique is illustrated on the multilayer perceptron with back-propagation learning. Dependency graphs have been given that represent the operations in the execution phases
The implementation of artificial neural networks into hardware will only show their true potential since the networks need full parallel processing for real-time applications. By this way neural networks are a genuine challenge to microelectronics: not only many synapses have to be integrated with a