SystemVerilog for Verification, Second Edition: A Guide to Learning the Testbench Language Features

✍ Scribed by Chris Spear

• Publisher: Springer
• Year: 2008
• Tongue: English
• Leaves: 455
• Edition: 2nd
• Category: Library

✦ Synopsis

The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

✦ Table of Contents

Cover......Page 1
System Verilog for Verification: A Guide to Learning the Testbench Language Features, Second Ed......Page 2
Copyright......Page 4
Contents......Page 6
List of Code Samples......Page 11
List of Figures......Page 23
List of Tables......Page 25
Preface......Page 26
Acknowledgments......Page 31
1 Verification Guidelines......Page 33
2 Data Types......Page 57
3 Procedural Statements and Routines......Page 94
4 Connecting the Testbench and Design......Page 109
5 Basic OOP......Page 155
6 Randomization......Page 190
7 Threads and Interprocess Communication......Page 246
8 Advanced OOP and Testbench Guidelines......Page 287
9 Functional Coverage......Page 323
10 Advanced Interfaces......Page 361
11 A Complete SystemVerilog Testbench......Page 379
12 Interfacing with C......Page 408
References......Page 447
Index......Page 449