SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications

✍ Scribed by Ashok B. Mehta (auth.)

• Publisher: Springer International Publishing
• Year: 2016
• Tongue: English
• Leaves: 424
• Edition: 2
• Category: Library

✦ Synopsis

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SystemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification using SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.

This updated second edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures.

· Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics;

· Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies;

· Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies;

· Explains each concept in a step-by-step fashion and applies it to a practical real life example;

· Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

✦ Table of Contents

Front Matter....Pages i-xxxv
Introduction....Pages 1-8
SystemVerilog Assertions....Pages 9-29
Immediate Assertions....Pages 31-34
Concurrent Assertions—Basics (Sequence, Property, Assert)....Pages 35-65
Sampled Value Functions $rose, $fell, $stable, $past....Pages 67-79
Operators....Pages 81-145
System Functions and Tasks....Pages 147-153
Multiple Clocks....Pages 155-166
Local Variables....Pages 167-180
Recursive Property....Pages 181-186
Detecting and Using Endpoint of a Sequence....Pages 187-199
‘expect’....Pages 201-203
‘assume’ and Formal (Static Functional) Verification....Pages 205-206
Very Important Topics and Applications....Pages 207-246
Asynchronous Assertions!!!....Pages 247-250
IEEE-1800-2009/2012 Features....Pages 251-303
SystemVerilog Assertions LABs....Pages 305-341
SystemVerilog Assertions—LAB Answers....Pages 343-360
Functional Coverage....Pages 361-366
Functional Coverage—Language Features....Pages 367-390
Performance Implications of Coverage Methodology....Pages 391-394
Coverage Options....Pages 395-401
Back Matter....Pages 403-406

✦ Subjects

Circuits and Systems; Electronics and Microelectronics, Instrumentation; Processor Architectures