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System-on-a-Chip Verification: Methodology and Techniques

โœ Scribed by Prakash Rashinkar, Peter Paterson, Leena Singh (auth.)

Publisher
Springer US
Year
2002
Tongue
English
Leaves
382
Edition
1
Category
Library
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โœฆ Synopsis

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

  1. Explanation of the objective involved in performing verification after a given design step;
  2. Features of options available;
  3. When to use a particular option;
  4. How to select an option; and
  5. Limitations of the option.
This exciting new book will be of interest to all designers and test professionals.

โœฆ Table of Contents

Introduction....Pages 1-43
System-level Verification....Pages 45-66
Block-level Verification....Pages 67-127
Analog/Mixed Signal Simulation....Pages 129-151
Simulation....Pages 153-234
Hardware/Software Co-verification....Pages 235-315
Static Netlist Verification....Pages 317-345
Physical Verification and Design Sign-off....Pages 347-358

โœฆ Subjects

Circuits and Systems; Computer-Aided Engineering (CAD, CAE) and Design; Computing Methodologies; Electronic and Computer Engineering

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