Synthesizable VHDL Design for FPGAs

✍ Scribed by Eduardo Augusto Bezerra, Djones Vinicius Lettnin

• Publisher: Springer
• Year: 2013
• Tongue: English
• Leaves: 161
• Category: Library

✦ Synopsis

The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. VHDL was first conceived as a documentation language for ASIC designs. Afterwards, the language was used for the behavioral simulation of ASICs, and also as a design input for synthesis tools. VHDL is a rich language, but just a small subset of it can be used to write synthesizable code, from which a physical circuit can be obtained. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools. The book introduces the subjects in a gradual and concise way, providing just enough information for the reader to develop their synthesizable digital systems in VHDL. The examples in the book were planned targeting an FPGA platform widely used around the world.

✦ Table of Contents

Contents
1 Digital Systems, FPGAs and the Design Flow
1.1…Digital Systems
1.2…Field Programmable Gate Array
1.3…FPGA Internal Organization
1.4…Configurable Logic Block
1.5…Electronic Design Automation and the FPGA Design Flow
1.6…FPGA Devices and Platforms
1.7…Writing Software for Microprocessors and VHDL Code for FPGAs
1.8…Laboratory Assignment
1.8.1 Logic Gates
1.8.2 Laboratory Session
2 HDL Based Designs
2.1…Theoretical Background
2.2…Laboratory Assignment
2.2.1 Laboratory Session
2.2.2 Going Beyond
3 Hierarchical Design
3.1…Hierarchical Design in VHDL
3.2…Laboratory Assignment
3.2.1 Laboratory Session
3.2.1.0 Step 1---Creating a New Project
3.2.1.0 Step 2---Adding VHDL Files to the Project
3.2.1.0 Step 3---Creating and Adding C3 to the Project
3.2.1.0 Step 4---Editing top.vhd to Add C3 to the Project
3.2.1.0 Step 5---Adapting the Design to Work in the DE2 FPGA Board
3.2.1.0 Step 6---Synthesis
3.2.1.0 Step 7---Simulation
3.2.1.0 Step 8---Prototyping the Circuit in the FPGA Board
4 Multiplexer and Demultiplexer
4.2…Laboratory Assignment
4.2.1 Laboratory Session
4.2.2 Version I: Multiplexer in Structural VHDL
4.2.3 Version II: Multiplexer in Behavioral VHDL
5 Code Converters
5.1…Arrays of Signals
5.2…Seven Segment Displays
5.3…Encoders and Decoders
5.4…Designing a Seven Segment Decoder
5.5…Case Study: A Simple but Fully Functional Calculator
5.6…Laboratory Assignment
6 Sequential Circuits, Latches and Flip-Flops
6.1…Sequential Circuits in VHDL: The Process Statement
6.2…Describing a D Latch in VHDL
6.3…Describing a D Flip-Flop in VHDL
6.4…Implementing Registers with D Flip-Flops
6.5…Laboratory Assignment
7 Synthesis of Finite State Machines
7.1…Finite State Machines
7.2…VHDL Synthesis of Finite State Machines
7.3…FSM Case Study: Designing a Counter
7.4…Laboratory Assignment
7.4.1 Laboratory Session
8 Using Finite State Machines as Controllers
8.1…Designing an FSM Based Control Unit
8.2…Case Study: Designing a Vending Machine Controller
8.3…Laboratory Assignment
8.3.1 Problem Definition: Calculator with Reduced Data Input Signals
8.3.2 Laboratory Session
8.3.3 Adding a New Input Register to the Calculator Design
8.3.4 Designing an FSM Based Controller for the Calculator
9 More on Processes and Registers
9.1…Implicit and Explicit Processes
9.2…Designing a Shift Register
9.3…Laboratory Assignment
9.3.1 Laboratory Session
10 Arithmetic Circuits
10.1…Half-Adder, Full-Adder, Ripple-Carry Adder
10.2…Laboratory Assignment
10.2.1 Laboratory Session
11 Writing Synthesizable VHDL Code for FPGAs
11.1…Synthesis and Simulation
11.2…VHDL Semantics for Synthesis
11.3…HDLGen: Automatic Generation of Synthesizable VHDL
Bibliography