<p><P><STRONG>Symbolic Simulation Methods for Industrial Formal Verification</STRONG> contains two distinct, but related, approaches to the verification problem. Both are based on symbolic simulation. The first approach is applied at the gate level and has been successful in verifying sub-circuits o
Symbolic Simulation Methods for Industrial Formal Verification
โ Scribed by Robert B. Jones (auth.)
- Publisher
- Springer US
- Year
- 2002
- Tongue
- English
- Leaves
- 158
- Edition
- 1
- Category
- Library
No coin nor oath required. For personal study only.
โฆ Synopsis
Symbolic Simulation Methods for Industrial Formal Verification contains two distinct, but related, approaches to the verification problem. Both are based on symbolic simulation. The first approach is applied at the gate level and has been successful in verifying sub-circuits of industrial microprocessors with tens and even hundreds of thousands of gates. The second approach is applied at a high-level of abstraction and is used for high-level descriptions of designs.
The book contains three main topics:
- Self consistency, a technique for deriving a formal specification of design behavior from the design itself;
- The use of the parametric representation to encode predicates as functional vectors for symbolic simulation, an important step in addressing the state-explosion problem;
- Incremental flushing, a method used to verify high-level descriptions of out-of-order execution.
โฆ Table of Contents
Front Matter....Pages i-xviii
Introduction....Pages 1-15
Front Matter....Pages 17-17
Self Consistency....Pages 19-33
Self Consistency in Practice....Pages 35-51
Front Matter....Pages 53-53
The Parametric Representation....Pages 55-71
Using the Parametric Representation....Pages 73-94
Front Matter....Pages 95-95
Background on Processor Verification....Pages 97-104
Incremental Flushing....Pages 105-123
Conclusions....Pages 125-126
Back Matter....Pages 127-151
โฆ Subjects
Circuits and Systems; Computing Methodologies; Computer-Aided Engineering (CAD, CAE) and Design; Electrical Engineering
๐ SIMILAR VOLUMES
Content: <br>Chapter 1 SPARK โ A Language and Tool?Set for High?Integrity Software Development (pages 1โ27): Ian O'Neill<br>Chapter 2 Model?Based Testing Automatic Generation of Test Cases Using the Markov Chain Model (pages 29โ81): Helene Le Guen, Frederique Vallee and Anthony Faucogney<br>Chapter
As digital logic designs grow larger and more complex, functional verification has become the number one bottleneck in the design process. Reducing verification time is crucial to project success, yet many practicing engineers have had little formal training in verification, and little exposure to t
<p><p>In his master thesis, Vladimir Herdt presents a novel approach, called complete symbolic simulation, for a more efficient verification of much larger (non-terminating) SystemC programs. The approach combines symbolic simulation with stateful model checking and allows to verify safety propertie