Substrate Noise Coupling in Mixed-Signal ASICs

✍ Scribed by Francois J. R. Clément (auth.), Stéphane Donnay, Georges Gielen (eds.)

• Publisher: Springer US
• Year: 2004
• Tongue: English
• Leaves: 310
• Edition: 1
• Category: Library

✦ Synopsis

This book is the first in a series of three dedicated to advanced topics in Mixed-Signal IC design methodologies. It is one of the results achieved by the Mixed-Signal Design Cluster, an initiative launched in 1998 as part of the TARDIS project, funded by the European Commission within the ESPRIT-IV Framework. This initiative aims to promote the development of new design and test methodologies for Mixed-Signal ICs, and to accelerate their adoption by industrial users. As Microelectronics evolves, Mixed-Signal techniques are gaining a significant importance due to the wide spread of applications where an analog front-end is needed to drive a complex digital-processing subsystem. In this sense, Analog and Mixed-Signal circuits are recognized as a bottleneck for the market acceptance of Systems-On-Chip, because of the inherent difficulties involved in the design and test of these circuits. Specially, problems arising from the use of a common substrate for analog and digital components are a main limiting factor. The Mixed-Signal Cluster has been formed by a group of 11 Research and Development projects, plus a specific action to promote the dissemination of design methodologies, techniques, and supporting tools developed within the Cluster projects. The whole action, ending in July 2002, has been assigned an overall budget of more than 8 million EURO.

✦ Table of Contents

Technology Impact on Substrate Noise....Pages 1-21
Substrate Noise Generation in Complex Digital Systems....Pages 23-45
Modeling and Analysis of Substrate Noise Coupling in Mixed-Signal ICs....Pages 47-63
SPACE for Substrate Resistance Extraction....Pages 65-92
Models and Parameters for Crosstalk Simulation....Pages 93-112
High-Level Simulation of Substrate Noise Generation in Complex Digitlal Systems....Pages 113-133
Modeling the Impact of Digital Substrate Noise on Analog Integrated Circuits....Pages 135-160
Measuring and Modeling the Effects of Substrate Noise on the LNA for a CMOS GPS Receiver....Pages 161-187
A Practical Approach to Modeling Silicon-Crosstalk in Systems-on-Silicon....Pages 189-208
The Reduction of Switching Noise Using CMOS Current Steering Logic....Pages 209-232
Low-Noise Digital Design Techniques....Pages 233-255
How to Deal with Substrate Bounce in Analog Circuits in Epi-Type CMOS Technology....Pages 257-269
Reducing Substrate Bounce in CMOS RF-Circuitry....Pages 271-287

✦ Subjects

Circuits and Systems; Electronic and Computer Engineering; Computer-Aided Engineering (CAD, CAE) and Design