𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Study of the influence of bias and matching networks on the distortion and memory of FET-based power amplifiers

✍ Scribed by Jon Santiago; Joaquín Portilla; Tomás Fernández

Book ID
102947305
Publisher
John Wiley and Sons
Year
2008
Tongue
English
Weight
735 KB
Volume
18
Category
Article
ISSN
1096-4290

No coin nor oath required. For personal study only.

✦ Synopsis

A study of the influence of bias and matching networks on the distortion and memory in FET-based power amplifiers has been carried out at the device and amplifier circuit levels. The study includes simulated and experimental results that allow us to identify effects produced by the introduction of particular biasing and matching networks in the power amplifier design. The influence of the bias point, as well as of biasing and matching network topologies on the nonlinear, short-and long-term memory behavior has been studied by means of simulations and measurements, using different power amplifier prototypes. V

📜 SIMILAR VOLUMES

Effect of gate-to-source capacitance of
Effect of gate-to-source capacitance of high-power Si-LDMOS FET on the asymmetrical intermodulation and modulation bandwidth of base-station amplifiers
✍ Younkyu Chung 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 141 KB

## Abstract This letter presents the effect of the gate‐to‐source capacitance (C~gs~) on the imbalance of the intermodulation distortion (IMD) and modulation bandwidth of Si‐LDMOS field effect transistor (FET) high‐power base‐station PAs. It is revealed that the strong C~gs~ nonlinearity at the inp

MMIC medium-power amplifier in K band wi
MMIC medium-power amplifier in K band with matching and power-divider/combiner networks implemented with the use of lumped elements
✍ L. Álvarez; J. Portilla; M.L. de la Fuente; E. Artal 📂 Article 📅 2002 🏛 John Wiley and Sons 🌐 English ⚖ 210 KB 👁 1 views

## Abstract The design and measurements of a monolithic K‐band medium‐power amplifier are reported. The matching, biasing, and power‐splitter networks have been implemented with the use of lumped elements, reducing the chip size. The model predictions of passive circuitry have been tested through e