Cover......Page 1
Half Title......Page 2
Title Page......Page 4
Copyright Page......Page 5
Dedication......Page 6
Table of Contents......Page 8
PREFACE......Page 18
1 INTRODUCTION......Page 24
1.1.1 Languages, Levels, and Virtual Machines......Page 25
1.1.2 Contemporary Multilevel Machines......Page 28
1.1.3 Evolutionof Multilevel Machines......Page 31
1.2.1 TheZeroth Generation—Mechanical Computers (1642–1945)......Page 36
1.2.2 The First Generation—Vacuum Tubes (1945–1955)......Page 39
1.2.3 The Second Generation—Transistors (1955–1965)......Page 42
1.2.4 The Third Generation—Integrated Circuits (1965–1980)......Page 44
1.2.5 The Fourth Generation—Very Large ScaleIntegration (1980–?)......Page 46
1.2.6 The Fifth Generation—Low-Power and Invisible Computers26......Page 49
1.3.1 Technological and Economic Forces......Page 51
1.3.2 The Computer Spectrum......Page 53
1.3.3 Disposable Computers......Page 54
1.3.4 Microcontrollers......Page 56
1.3.5 Mobileand Game Computers......Page 58
1.3.7 Servers......Page 59
1.3.8 Mainframes......Page 61
1.4.1 Introduction to the x86 Architecture......Page 62
1.4.2 Introduction to the ARM Architecture......Page 68
1.4.3 Introduction to the AVR Architecture......Page 70
1.5 METRICUNITS......Page 72
1.6 OUTLINE OF THIS BOOK......Page 73
2.1 PROCESSORS......Page 78
2.1.1 CPU Organization......Page 79
2.1.2 Instruction Execution......Page 81
2.1.3 RISC versus CISC......Page 85
2.1.4 Design Principles for Modern Computers......Page 86
2.1.5 Instruction-Level Parallelism......Page 88
2.1.6 Processor-Level Parallelism......Page 92
2.2 PRIMARY MEMORY......Page 96
2.2.2 Memory Addresses......Page 97
2.2.3 Byte Ordering......Page 99
2.2.4 Error-Correcting Codes......Page 101
2.2.5 Cache Memory......Page 105
2.2.6 Memory Packaging and Types......Page 108
2.3.1 Memory Hierarchies......Page 109
2.3.2 Magnetic Disks......Page 110
2.3.3 IDE Disks......Page 114
2.3.4 SCSI Disks......Page 115
2.3.5 RAID......Page 117
2.3.6 Solid-State Disks......Page 120
2.3.7 CD-ROMs......Page 122
2.3.8 CD-Recordables......Page 126
2.3.9 CD-Rewritables......Page 128
2.3.10 DVD......Page 129
2.4.1 Buses......Page 131
2.4.2 Terminals......Page 136
2.4.3 Mice......Page 141
2.4.4 Game Controllers......Page 143
2.4.5 Printers......Page 145
2.4.6 Telecommunications Equipment......Page 150
2.4.7 Digital Cameras......Page 158
2.4.8 Character Codes......Page 160
2.5 SUMMARY......Page 165
3.1 GATES AND BOOLEAN ALGEBRA......Page 170
3.1.1 Gates......Page 171
3.1.2 Boolean Algebra......Page 173
3.1.3 Implementation of Boolean Functions......Page 175
3.1.4 Circuit Equivalence......Page 176
3.2.1 Integrated Circuits......Page 181
3.2.2 Combinational Circuits......Page 182
3.2.3 Arithmetic Circuits......Page 186
3.2.4 Clocks......Page 191
3.3.1 Latches......Page 192
3.3.2 Flip-Flops......Page 195
3.3.4 Memory Organization......Page 197
3.3.5 Memory Chips......Page 201
3.3.6 RAMs and ROMs......Page 203
3.4.1 CPU Chips......Page 208
3.4.2 Computer Buses......Page 210
3.4.3 Bus Width......Page 213
3.4.4 Bus Clocking......Page 214
3.4.5 Bus Arbitration......Page 219
3.4.6 Bus Operations......Page 221
3.5.1 The Intel Corei7......Page 224
3.5.2 The Texas Instruments OMAP4430 System-on-a-Chip......Page 231
3.5.3 The Atmel ATmega168 Microcontroller......Page 235
3.6 EXAMPLE BUSES......Page 237
3.6.1 The PCI Bus......Page 238
3.6.2 PCI Express......Page 246
3.6.3 The Universal Serial Bus......Page 251
3.7.1 I/O Interfaces......Page 255
3.7.2 Address Decoding......Page 256
3.8 SUMMARY......Page 258
4.1 AN EXAMPLE MICRO ARCHITECTURE......Page 264
4.1.1 The Data Path......Page 265
4.1.2 Microinstructions......Page 272
4.1.3 Microinstruction Control: TheMic-1......Page 274
4.2.1 Stacks......Page 279
4.2.2 The IJVM Memory Model......Page 281
4.2.3 The IJVM Instruction Set......Page 283
4.2.4 Compiling Java to IJVM......Page 286
4.3.1 Microinstructions and Notation......Page 288
4.3.2 Implementation of IJVM Using the Mic-1......Page 292
4.4.1 Speed versus Cost......Page 304
4.4.2 Reducing the Execution Path Length......Page 306
4.4.3 A Design with Prefetching: The Mic-2......Page 312
4.4.4 A Pipelined Design: The Mic-3......Page 314
4.4.5 A Seven-Stage Pipeline: The Mic-4......Page 321
4.5 IMPROVING PERFORMANCE......Page 324
4.5.1 Cache Memory......Page 325
4.5.2 Branch Prediction......Page 331
4.5.3 Out-of-Order Execution and Register Renaming......Page 336
4.5.4 Speculative Execution......Page 341
4.6.1 The Microarchitecture of the Corei7 CPU......Page 344
4.6.2 The Microarchitecture of the OMAP4430 CPU......Page 350
4.6.3 The Microarchitecture of the ATmega168 Microcontroller......Page 355
4.7 COMPARISON OF THE I7, OMAP4430, AND ATMEGA168......Page 357
4.8 SUMMARY......Page 358
5 THE INSTRUCTION SET LEVEL......Page 362
5.1.1 Properties of the ISA Level......Page 364
5.1.2 Memory Models......Page 366
5.1.3 Registers......Page 368
5.1.5 Overview of the Core i7 ISA Level......Page 370
5.1.6 Overview of the OMAP4430 ARMISA Level......Page 373
5.1.7 Overview of the ATmega168 AVRISA Level......Page 375
5.2.1 Numeric Data Types......Page 377
5.2.2 Nonnumeric Data Types......Page 378
5.2.3 Data Types on the Corei7......Page 379
5.2.5 Data Types on the ATmega168 AVR CPU......Page 380
5.3.1 Design Criteria for Instruction Formats......Page 381
5.3.2 Expanding Opcodes......Page 384
5.3.3 The Core i7 Instruction Formats......Page 386
5.3.4 The OMAP4430 ARM CPU Instruction Formats......Page 387
5.3.5 The ATmega168 AVR Instruction Formats......Page 389
5.4.1 Addressing Modes......Page 390
5.4.4 Register Addressing......Page 391
5.4.5 Register Indirect Addressing......Page 392
5.4.6 Indexed Addressing......Page 393
5.4.8 Stack Addressing......Page 395
5.4.9 Addressing Modes for BranchInstructions......Page 398
5.4.10 Orthogonality of Opcodes and Addressing Modes......Page 399
5.4.11 The Core i7 Addressing Modes......Page 401
5.4.13 The ATmega168 AVR Addressing Modes......Page 403
5.4.14 Discussion of Addressing Modes......Page 404
5.5.1 Data Movement Instructions......Page 405
5.5.2 Dyadic Operations......Page 406
5.5.3 Monadic Operations......Page 407
5.5.4 Comparisons and Conditional Branches......Page 409
5.5.5 Procedure Call Instructions......Page 411
5.5.6 Loop Control......Page 412
5.5.7 Input/Output......Page 413
5.5.8 The Core i7 Instructions......Page 416
5.5.9 The OMAP4430 ARM CPU Instructions......Page 419
5.5.11 Comparison of Instruction Sets......Page 421
5.6 FLOW OF CONTROL......Page 423
5.6.1 Sequential Flow of Control and Branches......Page 424
5.6.2 Procedures......Page 425
5.6.3 Coroutines......Page 429
5.6.4 Traps......Page 432
5.6.5 Interrupts......Page 433
5.7 A DETAILED EXAMPLE: THE TOWERS OF HANOI......Page 436
5.7.2 The Towers of Hanoi in OMAP4430 ARM Assembly Language......Page 437
5.8 THE IA-64 ARCHITECTURE AND THE ITANIUM......Page 439
5.8.1 The Problem with the IA-32 ISA......Page 440
5.8.3 Reducing Memory References......Page 442
5.8.4 Instruction Scheduling......Page 443
5.8.5 Reducing Conditional Branches: Predication......Page 445
5.8.6 Speculative Loads......Page 448
5.9 SUMMARY......Page 449
6 THE OPERATING SYSTEM THE OPERATING SYSTEM MACHINE LEVEL......Page 454
6.1 VIRTUAL MEMORY......Page 455
6.1.1 Paging......Page 456
6.1.2 Implementation of Paging......Page 458
6.1.3 Demand Paging and the Working-Set Model......Page 460
6.1.4 Page-Replacement Policy......Page 463
6.1.5 Page Size and Fragmentation......Page 465
6.1.6 Segmentation......Page 466
6.1.7 Implementation of Segmentation......Page 469
6.1.8 Virtual Memory on the Core i7......Page 472
6.1.9 Virtual Memory on the OMAP4430 ARM CPU......Page 477
6.1.10 Virtual Memory and Caching......Page 479
6.2 HARDWARE VIRTUALIZATION......Page 480
6.2.1 Hardware Virtualization on the Core I7......Page 481
6.3.1 Files......Page 482
6.3.2 Implementation of OSM-Level I/O Instructions......Page 484
6.4 OSM-LEVEL INSTRUCTIONS FOR PARALLEL PROCESSING......Page 488
6.4.2 Race Conditions......Page 490
6.4.3 Process Synchronization Using Semaphores......Page 495
6.5 EXAMPLE OPERATING SYSTEMS......Page 497
6.5.1 Introduction......Page 499
6.5.2 Examples of Virtual Memory......Page 505
6.5.3 Examples of OS-Level I/O......Page 509
6.5.4 Examples of Process Management......Page 520
6.6 SUMMARY......Page 526
7 THE ASSEMBLY LANGUAGE LEVEL......Page 532
7.1.1 What Is an Assembly Language?......Page 533
7.1.2 Why Use Assembly Language?......Page 534
7.1.3 Format of an Assembly Language Statement......Page 535
7.1.4 Pseudoinstructions......Page 537
7.2.1 Macro Definition, Call, and Expansion......Page 539
7.2.2 Macroswith Parameters......Page 541
7.2.3 Advanced Features......Page 542
7.2.4 Implementation of a Macro Facility in an Assembler......Page 543
7.3.1 Two-Pass Assemblers......Page 544
7.3.2 Pass One......Page 545
7.3.3 Pass Two......Page 549
7.3.4 The Symbol Table......Page 550
7.4 LINKING AND LOADING......Page 551
7.4.1 Tasks Performed by the Linker......Page 553
7.4.2 Structure of an Object Module......Page 556
7.4.3 Binding Time and Dynamic Relocation......Page 557
7.4.4 Dynamic Linking......Page 560
7.5 SUMMARY......Page 564
8 PARALLEL COMPUTER ARCHITECTURES......Page 568
8.1 ON-CHIP PARALELLISM......Page 569
8.1.1 Instruction-Level Parallelism......Page 570
8.1.2 On-Chip Multithreading......Page 577
8.1.3 Single-Chip Multiprocessors......Page 583
8.2.1 Network Processors......Page 589
8.2.2 Graphics Processors......Page 597
8.2.3 Cryptoprocessors......Page 600
8.3.1 Multiprocessors vs. Multicomputers......Page 601
8.3.2 Memory Semantics......Page 608
8.3.3 UMA Symmetric Multiprocessor Architectures......Page 613
8.3.4 NUMA Multiprocessors......Page 621
8.3.5 COMA Multiprocessors......Page 629
8.4 MESSAGE-PASSING MULTICOMPUTERS......Page 631
8.4.1 Interconnection Networks......Page 632
8.4.2 MPPs—Massively Parallel Processors......Page 636
8.4.3 Cluster Computing......Page 646
8.4.4 Communication Software for Multicomputers......Page 651
8.4.5 Scheduling......Page 654
8.4.6 Application-Level Shared Memory......Page 655
8.4.7 Performance......Page 661
8.5 GRID COMPUTING......Page 667
8.6 SUMMARY......Page 670
9 BIBLIOGRAPHY......Page 674
A.1 FINITE-PRECISION NUMBERS......Page 684
A.2 RADIX NUMBER SYSTEMS......Page 686
A.3 CONVERSION FROM ONE RADIX TO ANOTHER......Page 688
A.4 NEGATIVE BINARY NUMBERS......Page 690
A.5 BINARY ARITHMETIC......Page 693
B FLOATING-POINT NUMBERS......Page 696
B.1 PRINCIPLES OF FLOATING POINT......Page 697
B.2 IEEE FLOATING-POINT STANDARD......Page 699
C ASSEMBLY LANGUAGE PROGRAMMING......Page 706
C.1.1 Assembly Language......Page 707
C.1.2 ASmall Assembly Language Program......Page 708
C.2 THE 8088 PROCESSOR......Page 709
C.2.2 TheGeneral Registers......Page 710
C.2.3 Pointer Registers......Page 713
C.3.1 Memory Organization and Segments......Page 714
C.3.2 Addressing......Page 716
C.4.1 Move, Copy and Arithmetic......Page 720
C.4.3 Loop and Repetitive String Operations......Page 723
C.4.4 Jump and Call Instructions......Page 724
C.4.5 Subroutine Calls......Page 725
C.4.6 System Calls and System Subroutines......Page 727
C.5.1 Introduction......Page 730
C.5.2 The ACK-Based Tutorial Assembler as88......Page 731
C.5.3 Some Differences with Other 8088 Assemblers......Page 735
C.6 THE TRACER......Page 736
C.6.1 Tracer Commands......Page 738
C.7 GETTING STARTED......Page 740
C.8.1 Hello World Example......Page 741
C.8.2 General Registers Example......Page 744
C.8.3 Call Command and Pointer Registers......Page 745
C.8.4 Debugging an Array Print Program......Page 749
C.8.5 String Manipulation and String Instructions......Page 751
C.8.6 Dispatch Tables......Page 755
C.8.7 Buffered and Random File Access......Page 757
INDEX......Page 762
Back Cover......Page 786