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Custom IC (integrated circuit) design at GEC Semiconductors has been enhanced by a new service called CELLMOS. Using this, customers design their own ICs with standard cells and circuits from a library.
Designs are built up using the characteristics of 4000-series CMOS logic parts. Once this has been achieved, CELLMOS provides a complete logic diagram of the system, naming each connection. Lists of the logic are also output, along with a set of test waveform definitions if required.
This data is then entered into GEC's 4070 computer for compatability checks. If waveform definitions are supplied, a logic simulation of the circuit is also performed.
Once all this data has been verified, a layout program optimizes cell placements and interconnections and then generates a plot of the complete chip, and a plot of the logic for verification.
This design loop is repeated until the IC is certified correct, then the layout is simply transferred into magnetic tape format for preparing production masks.
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