Techniques to reduce or tolerate large memory latencies are critical for achieving high processor performance. Hardware data prefetching is one of the most heavily studied solutions, but it is essentially applied to first-level caches where it can severely disrupt processor behavior by delaying norm
β¦ LIBER β¦
Stride prefetching for the secondary data cache
β Scribed by Ando Ki; Alan E. Knowles
- Publisher
- Elsevier Science
- Year
- 2000
- Tongue
- English
- Weight
- 287 KB
- Volume
- 46
- Category
- Article
- ISSN
- 1383-7621
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