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Sizing of cell-level analog circuits using constrained optimization techniques

✍ Scribed by Maulik, P.C.; Carley, L.R.; Allstot, D.J.

Book ID: 119773770
Publisher: IEEE
Year: 1993
Tongue: English
Weight: 1012 KB
Volume: 28
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.209989

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