Numerical simulations were performed to investigate convective±conductive heat transfer due to a laminar boundary layer ¯ow of air over a two dimensional array of rectangular chip blocks which represent the ®nite heat sources. The main focus of this study is on the simulation of the ¯ow ®elds and temperature variations of the air and the chip blocks. The purpose of this study is to verify the eects of the openings of the board in the areas between the chip blocks on the enhancement of cooling the heating blocks. Due to a pressure dierential occurring across the opening, the induced vertical ¯ow serves as a suction or blowing force and consequently enhances heat dissipation to the ambient ¯uid. The optimal con®guration of the chip board regarding cooling the heat source would yield lower chip temperatures with limited chip-to-chip temperature variations.
A time-accurate numerical scheme algorithm, PISO (pressure-implicit with splitting of operators), is used to simulate the conjugate heat transfer between the ¯uid and solid phases. In this work, a set of false solid properties was employed to force the solid side to have a time scale comparable to that of the ¯uid side in order to avoid numerical instabilities due to dierent time scales used in the calculations. The results of the simulations show that the existence of the array of blocks results in stagnant ¯ow regions between blocks in which heat convected to the ambient ¯ow ®eld is limited. It was found that heat transfer can be enhanced passively, especially in the areas between blocks, by opening the chip board between blocks. The enhancement of heat transfer thus occurring is presumably due to a pseudo-suction force which induces a vertical ¯ow between blocks. The enhancement of heat transfer for the chips on-board is re¯ected by a global increase of the Nusselt number on the chip blocks, especially on the west sides of the chips located further downstream of the ¯ow direction. Further investigation shows that the chip-to-chip temperature variations diminish if the openings located upstream of the front end block and downstream of the rear end block are sealed. The optimal cooling con®guration for the array of chip blocks can be utilized by the electronics industry.