Silicon-on-insulator (SOI) technology: Manufacture and applications

✍ Scribed by Kononchuk, Oleg(Editor);Nguyen, Bich-Yen(Editor)

• Publisher: Woodhead Publishing
• Year: 2014
• Tongue: English
• Leaves: 219
• Category: Library

✦ Synopsis

Silicon-on-insulator (SOI) is a semiconductor wafer technology that produces higher performing, lower power devices than traditional bulk silicon techniques. SOI works by placing a thin, insulating layer, such as silicon oxide between a thin layer of silicon and the silicon substrate. This process helps reduce junction capacitance, resulting in higher speed and lower power consumption. SOI chips can be as much as 15 percent faster and use 20 percent less power than today’s silicon complementary metal-oxide semiconductor (CMOS)-based chips. Part one covers SOI transistors and circuits, manufacture and reliability and part two looks at applications such as memory, power devices and photonics.

✦ Table of Contents

Front Cover......Page 1
Industry Standard FDSOI Compact Model BSIM-IMG for IC Design......Page 4
Copyright Page......Page 5
Contents......Page 6
List of Contributors......Page 10
1.1 Silicon on Oxide and Pre-2010 SOI CMOS Transistor......Page 12
1.2 What Limits the Scaling of the Bulk and PDSOI CMOS Transistors?......Page 14
1.3 The Ultrathin-Body Concept and Ultrathin-Body Fully Depleted SOI......Page 16
1.4 Comparison of FDSOI with FinFET and Other Ultrathin-Body Transistors......Page 20
1.5 Compact Model—The Bridge Between FDSOI Device/Technology and IC Design......Page 21
References......Page 24
2.1 Introduction......Page 26
2.2 Independent Multigate MOSFETs......Page 27
2.3 Core Model......Page 29
2.3.1 Fast Core Model......Page 30
2.3.1.1 Calculation of Surface Potential in Fast Core Model......Page 31
2.3.2 Extended Range Model......Page 34
2.4 Core Model Analytical Solution......Page 37
2.5 Drain Current Model......Page 39
2.6 Terminal Charge Model......Page 41
References......Page 44
3.2 Vertical Field Dependence of Carrier Mobility......Page 46
3.2.1 Nonmonotonic Back-Gate Bias Dependence of Mobility......Page 48
3.3 Threshold Voltage......Page 50
3.3.1 Short-Channel Effects......Page 52
3.3.2 Drain-Induced Barrier Lowering......Page 53
3.3.3 Reverse Short-Channel Effect......Page 54
3.3.4 Threshold Voltage Roll-Off at Moderate Channel Length......Page 55
3.3.6 Effect of Substrate Depletion on Threshold Voltage......Page 56
3.3.7 Operating Point Threshold Voltage......Page 59
3.4 Drain Saturation Voltage......Page 62
3.4.2 When RDSMOD=1......Page 66
3.5 Quantum Mechanical Effects......Page 67
3.7.1 Channel-Length Modulation......Page 68
3.7.2 Output Conductance Due to Drain-Induced Barrier Lowering......Page 69
3.8 Velocity Saturation Effect......Page 70
3.9 Series Resistance Model......Page 71
3.9.2 Bias-Dependent Source/Drain Resistance......Page 72
References......Page 73
4.1.1 Subthreshold Leakage......Page 76
4.1.2 Gate-Induced Source and Drain Leakage Model......Page 77
4.1.3 Gate Oxide Leakage......Page 79
4.1.3.1 Gate-to-Body Tunneling Current......Page 80
4.1.3.2 Gate-to-Channel Tunneling Current......Page 81
4.1.3.3 Gate-to-Source (Drain) Tunneling Current......Page 82
4.2.1 Modeling of Self-Heating Effect......Page 83
4.2.2 Temperature Dependence of Parameters......Page 87
4.2.2.3 Temperature Dependence of Nc, Vbi, ΦB, and ΦSUB......Page 88
4.2.2.5 Temperature Dependence of Mobility......Page 89
4.2.2.7 Temperature Dependence of Velocity Saturation......Page 92
4.2.2.9 Temperature Dependence of Parasitic Source/Drain Resistances......Page 93
4.2.3 Impact of Ambient Temperature on Thermal Resistance......Page 94
4.2.4 Frequency Dependence of Self-Heating Effect......Page 95
4.2.4.1 Extraction of Rth, Cth......Page 96
References......Page 97
5.1 Introduction......Page 100
5.2 Capacitance Calculation From Terminal Charges......Page 101
5.3.1 Terminal Charges in Fast Core Model......Page 104
5.3.2 Intrinsic Charge Model in Extended Range Core Model......Page 107
5.4 Modeling the Impact of Real Device Effects on Terminal Charges......Page 109
5.4.1 Impact of Mobility Degradation......Page 110
5.4.2 Impact of Pinch-Off and Velocity Saturation......Page 111
5.4.3 Impact of Channel-Length Modulation......Page 112
5.5.1 Outer Fringe Capacitance......Page 113
5.5.2 Overlap Capacitance Model......Page 114
5.5.3 Source/Drain to Substrate Fringe Capacitance......Page 115
References......Page 116
6.1 Background......Page 118
6.1.1 First Step of Parameter Extraction......Page 119
6.2.2.1 Subthreshold Region......Page 120
6.2.2.2 Strong-Inversion Region......Page 121
6.2.3.2 Strong-Inversion Region......Page 122
6.2.5 Note on Back Bias Effect on Threshold Voltage......Page 123
6.3 Short-Channel Device Extraction and Length Scaling......Page 125
6.4.1 Gate-Induced Drain Leakage......Page 127
6.4.2.1 Accumulation to Weak-Inversion Region......Page 130
6.5 Extraction of Temperature Dependence Parameters......Page 131
6.5.1 Length Scaling of Temperature Parameters......Page 133
References......Page 134
7.1 Symmetry Tests......Page 136
7.1.1 Gummel Symmetry Test......Page 137
7.1.2 AC Symmetry Test......Page 139
7.2.1 Conductance Test......Page 141
7.2.2 Slope Ratio Test......Page 143
7.2.3 Volume Inversion Test......Page 144
7.3 Test for Self-Heating Effect......Page 145
7.4.1 Modeling the Germanium on Insulator FD-SOI......Page 147
7.4.2 Model Results and Circuit Level Validation......Page 151
7.4.3 Germanium on Insulator-Based CMOS Inverter......Page 152
References......Page 154
8 High-Frequency and Noise Models in BSIM-IMG......Page 156
8.1 Radio-Frequency Characterization......Page 157
8.2.1 Thermal Resistance Network......Page 161
8.2.2 Substrate Parasitic Network......Page 166
8.2.3 Gate Parasitic Network......Page 168
8.2.3.1 Gate Capacitance Network......Page 169
8.3 Noise Models......Page 170
8.3.1 Thermal Noise Model......Page 173
8.4 Thermal Noise Characterization......Page 177
8.4.1 Thermal Noise Parameters......Page 179
8.5 Model Validation......Page 182
8.5.1 Experimental Validation of High-Frequency Noise Parameters......Page 184
8.5.2 Asymptotic Behavior of Model......Page 187
8.6 Induced Gate Thermal Noise Model......Page 190
8.6.1 Flicker Noise Model......Page 196
8.6.2 Other Noise Components......Page 200
8.7.2 Derivation for Relation Between dqf and dV......Page 201
8.7.3 Derivation for Relation Between dqb and dV......Page 203
References......Page 204
Index......Page 212
Back Cover......Page 219