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Sequential logic optimization for low power using input-disabling precomputation architectures

✍ Scribed by Monteiro, J.; Devadas, S.; Ghosh, A.

Book ID: 119778315
Publisher: IEEE
Year: 1998
Tongue: English
Weight: 159 KB
Volume: 17
Category: Article
ISSN: 0278-0070
DOI: 10.1109/43.700725

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