Cover
Half Title
Title Page
Copyright Page
Dedication
Table of Contents
Preface
Acknowledgments
Author
Chapter 1: Semiconductor Memory Technologies Overview
1.1 Introduction to Memory Hierarchy
1.1.1 Data Explosion to Zetta-scale
1.1.2 Memory Hierarchy in the Memory Sub-system
1.2 Semiconductor Memory Industry Landscape
1.3 Introduction to Memory Array Architecture
1.3.1 Generic Memory Array Diagram
1.3.2 Memory Cell Size and Equivalent Bit Area
1.3.3 Memory Arrayโs Area Efficiency
1.3.4 Peripheral Circuits: Decoder, MUX, and Driver
1.3.5 Peripheral Circuits: Sense Amplifier
1.4 Industry Technology Scaling Trend
1.4.1 Mooreโs Law and Logic Scaling Trend
1.4.2 Definition of Technology Node and Metric for Integration Density
1.5 Logic Transistor Technology Evolution
Notes
References
Chapter 2: Static Random Access Memory (SRAM)
2.1 6T SRAM Cell Operation
2.1.1 SRAM Array and 6T Cell
2.1.2 Principles of Hold, Read and Write
2.2 SRAM Stability Analysis
2.2.1 Static Noise Margin
2.2.2 N-curve
2.2.3 Dynamic Noise Margin
2.2.4 Read/Write-Assist Schemes
2.3 SRAMโs Leakage
2.3.1 Transistorโs Sub-threshold Current
2.3.2 SRAMโs Leakage Reduction
2.4 Variability and Reliability
2.4.1 Transistor Intrinsic Parameter Fluctuations and the Impact on SRAM Stability
2.4.2 Temporal Reliability Issues and the Impact on SRAM Stability
2.4.3 Soft Error Caused by Radiation Effects
2.5 SRAM Layout and Scaling Trend
2.5.1 6T Cell Layout
2.5.2 SRAM Scaling Trend
2.6 FinFET-Based SRAM
2.6.1 FinFET Technology
2.6.2 SRAM Scaling in FinFET Era
Notes
References
Chapter 3: Dynamic Random Access Memory (DRAM)
3.1 DRAM Overview
3.1.1 DRAM Sub-system Hierarchy
3.1.2 DRAM I/O Interface
3.2 1T1C DRAM Cell Operation
3.2.1 Principle of 1T1C Cell
3.2.2 Charge Sharing and Sensing
3.2.3 DRAM Leakage and Refresh
3.3 DRAM Technology
3.3.1 Trench Capacitor and Stacked Capacitor
3.3.2 DRAM Array Architecture
3.3.3 DRAM Layout
3.4 DRAM Scaling Trend
3.4.1 Scaling Challenges
3.4.2 Cell Capacitor
3.4.3 Interconnect
3.4.4 Cell Access Transistor
3.5 3D Stacked DRAM
3.5.1 TSV Technology and Heterogeneous Integration
3.5.2 HBM
3.6 Embedded DRAM
3.6.1 1T1C eDRAM
3.6.2 Capacitor-Less eDRAM
Notes
References
Chapter 4: Flash Memory
4.1 Flash Overview
4.1.1 Flashโs History
4.1.2 Flashโs Applications
4.2 Flash Device Physics
4.2.1 Principle of Floating-Gate Transistor
4.2.2 Capacitor Model for Floating-Gate Transistor
4.2.3 Program/Erase Mechanism
4.2.4 Source-side Injection for Embedded Flash
4.3 Flash Array Architectures
4.3.1 NOR Array
4.3.2 NAND Array
4.3.3 Peripheral Circuits for High Voltage
4.3.4 NAND Flash Translation Layer
4.3.5 Comparison between NOR and NAND
4.4 Multilevel Cell
4.4.1 Multi-level Cell (MLC) Basics
4.4.2 Incremental Step Pulse Programming (ISPP)
4.5 Flash Reliability
4.5.1 Endurance
4.5.2 Retention
4.5.3 Disturb
4.5.4 Trade-offs between Reliability Effects
4.6 Flash Scaling Challenges
4.6.1 Cell-to-Cell Interference
4.6.2 Few Electrons Problem
4.7 3D NAND Flash
4.7.1 Principle of Charge-trap Transistor
4.7.2 Cost-Effective 3D Integration Approaches
4.7.3 3D NAND Fabrication Issues
4.7.4 Analysis of the First-generation 3D NAND Chip
4.7.5 New Trends in 3D NAND
Notes
References
Chapter 5: Emerging Non-volatile Memories
5.1 eNVM Overview
5.1.1 Landscape of eNVMs
5.1.2 1T1R Array
5.1.3 Cross-Point Array and Selector
5.2 Phase Change Memory (PCM)
5.2.1 PCM Device Physics
5.2.2 Reliability of PCM
5.2.3 Array Integration of PCM
5.2.4 3D X-point
5.3 Resistive Random Access Memory (RRAM)
5.3.1 RRAM Device Physics
5.3.2 Reliability of RRAM
5.3.3 Array Integration of RRAM
5.4 Magnetic Random Access Memory (MRAM)
5.4.1 MTJ Device Physics
5.4.2 Field Switching MRAM
5.4.3 STT-MRAM
5.4.4 SOT-MRAM
5.5 Ferroelectric Memories
5.5.1 Ferroelectrics Device Physics
5.5.2 1T1C FeRAM
5.5.3 FeFET
5.6 Compute-in-Memory
5.6.1 Principle of CIM
5.6.2 Synaptic Device Properties
5.6.3 CIM Prototype Chips
Notes
References
Index