New results are given on the phenomenon of false lock in second-order, Type I phase locked loops (PLLs) with a constant frequency reference of wi and a voltage controlled oscillator (VCO) quiescent frequency of wO. This loop has on[v one false lock state whose frequency error approaches Wi -co0 as Ioop gain 6 approaches zero, and this false lock state is stable. This false lock state corresponds to a stable, hyperbolic limit cycle X,(t ; 6) of the nonlinear equation describing the loop. As gain 6 is increasedfrom a value of zero, it is shown that a value 6, can be reached where X,Y becomes semi-stable and nonhyperbolic. Furthermore, saddle node bifurcation occurs at 6,, and a second limit cycle X,(t; 6) branches from this bifurcation point. Limit cycle X, is unstable, and it corresponds to an unstable false lock state of the PLL. Furthermore, X, can be continued as a function of gain on an interval o2 < 6 < 6,, for some 6, > 0. Finally, ZXY and X, do not exist for 6 > 6,. Two numerical algorithms are given to anaIyse the faIse locked PLL under consideration.
The first is useful for computing the above-mentioned limit cycles and the bifurcation point 6,. The second algorithm can calculate a Poincare map and its derivative which are useful in studying the saddle node bifurcation which occurs at 6 ,. Also given is a detailed decription of a laboratory experiment which was used to substantiate the theory and numerical techniques. The quahtative theory, numerical method and laboratory procedure are applied to a simple example. The numerical and empirical results are shown to be in close agreement.