Reduction of complex MOS structures used in switch-level simulators

✍ Scribed by Cherif Aissi; Desa Gobovic

• Book ID: 104157856
• Publisher: Elsevier Science
• Year: 1998
• Tongue: English
• Weight: 528 KB
• Volume: 29
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/s0026-2692(97)00089-x

✦ Synopsis

The ratio of a transistor's width to its length is the only geometric parameter available to design engineers that affects the performance of a MOS transistor. This ratio, known also as the shape factor, defines the transistor strength. Most switch-level simulators are built with knowledge of the transistor strength. In this paper, a theory that will provide a method for calculating the equivalent transistor strength (shape factor) of complex MOS transistor structures is developed. In the case of non-series-parallel MOS structures, this method includes a Y-to-A transformation which usu~dly leads to a significant reduction of circuit complexity. The results obtained are applicable to both NMOS and CMOS structures. The method introduced is illustrated by examples. Computer simulation is also used to show the validity and effectiveness of the results obtained.