Real World FPGA Design with Verilog [With CDROM]

✍ Scribed by Coffman, Ken

• Publisher: Prentice Hall
• Year: 1999
• Tongue: English
• Leaves: 316
• Category: Library

✦ Synopsis

The practical guide for every circuit designer creating FPGA designs with Verilog Walk through design step-by-step-from coding through silicon. Partitioning, synthesis, simulation, test benches, combinatorial and sequential designs, and more. Real World FPGA Design with Verilog guides you through every key challenge associated with designing FPGAs and ASICs using Verilog, one of the world's leading hardware design languages. You'll find irreverent, yet rigorous coverage of what it really takes to translate HDL code into hardware-and how to avoid the pitfalls that can occur along the way. Ken Coffman presents no-frills, real-world design techniques that can improve the stability and reliability of virtually any design. Start by walking a typical Verilog design all the way through to silicon; then, review basic Verilog syntax, design; simulation and testing, advanced simulation, and more. Coverage includes:Essential digital design strategies: recognizing the underlying analog building blocks used to create digital primitives; implementing logic with LUTs; clocking strategies, logic minimization, and moreKey engineering tradeoffs, including operating speed vs. latencyCombinatorial and sequential designsVerilog test fixtures: compiler directives and automated testingA detailed comparison of alternative architectures and software-including a never-before-published FPGA technology selection checklistReal World FPGA Design with Verilog introduces libraries and reusable modules, points out opportunities to reuse your own code, and helps you decide when to purchase existing IP designs instead of building from scratch. Essential rules for designing with ASIC conversion in mind are presented. If you're involved with digital hardware design with Verilog, Ken Coffman is a welcome voice of experience-showing you the shortcuts, helping you over the rough spots, and helping you achieve competence faster than you ever expected

✦ Table of Contents

Cover......Page 1
Contents......Page 6
Foreword: Notes on the Current State of the Art......Page 10
Preface: Digital Design in the Real World......Page 12
Acknowledgments......Page 16
Notes on the Second Printing......Page 18
Chapter 1 Verilog Design in the Real World......Page 20
Trivial Overheat Detector Example......Page 23
Synthesizable Verilog Elements......Page 27
Verilog Hierarchy......Page 31
Built-In Logic Primitives......Page 33
Latches and Flipflops......Page 38
Blocking and Nonblocking Assignments......Page 44
Miscellaneous Verilog Syntax Items......Page 48
Design Processing Steps......Page 60
Analog Building Blocks for Digital Primitives......Page 61
Using a LUT to Implement Logic Functions......Page 63
Discussion of Design Processing Steps......Page 66
Synchronous Logic Rules......Page 76
Clocking Strategies......Page 83
Logic Minimization......Page 86
What Does the Synthesizer Do?......Page 90
Area/Delay Optimization......Page 93
Verilog Hierarchy Revisited......Page 96
Tristate Signals and Busses......Page 97
Bidirectional Busses......Page 102
Priority Encoders......Page 103
Area/Speed Optimization in Synthesis......Page 108
Trade-off Between Operating Speed and Latency......Page 112
Delays in FPGA Logic Elements......Page 114
State Machines......Page 116
Adders......Page 126
Subtractors......Page 135
Multipliers......Page 136
Ripple Counters......Page 142
Johnson Counters......Page 143
Linear Feedback Shift Registers......Page 146
Cyclic Redundancy Checksums......Page 154
ROM......Page 156
RAM......Page 158
FIFO Notes......Page 174
Chapter 5 Verilog Test Fixtures......Page 176
Compiler Directives......Page 177
Automated Testing......Page 190
Chapter 6 Real World Design: Tools, Techniques, and Trade-offs......Page 196
Compiling with LeonardoSpectrum......Page 198
Complete Design Flow, 8-Bit Equality Comparator......Page 208
8-Bit Equality Comparator with Hierarchy......Page 214
Optimization Options In the Xilinx Environment......Page 223
Mapping Options......Page 224
Logic Level Timing Report/Post Layout Timing Report......Page 228
VHDL/Verilog Simulation Options......Page 231
Other Design Manager Tools......Page 234
Factors that Determine Integrated Circuit Pricing......Page 242
FPGA Device Design......Page 243
FPGA Technology Selection Checklist......Page 245
Xilinx FPGA Architectures......Page 247
Altera CPLD Architectures......Page 254
Chapter 8 Libraries, Reusable Modules, and IP......Page 258
Keys to Increased Productivity......Page 259
Library Elements......Page 261
Structural Coding Style......Page 266
A Small Diversion to Compare a Schematic to a Verilog Design......Page 267
Using LogiBLOX Module Generator......Page 270
Design Reuse, Reusing Your Own Code......Page 275
Buying IP Designs......Page 277
Summing Up......Page 278
Chapter 9 Designing for ASIC Conversion......Page 280
HardCopy Devices......Page 281
Semicustom Devices......Page 282
Design Rules for ASIC Conversion......Page 284
Synchronous Design Rules......Page 285
Oscillators......Page 287
Delay Lines......Page 288
The Language of Test......Page 290
Print-on-Change Test Vectors......Page 292
Afterword—A Look into the Future......Page 294
Resources......Page 296
B......Page 298
C......Page 299
F......Page 301
G......Page 302
I......Page 303
N......Page 304
P......Page 305
R......Page 306
S......Page 307
V......Page 308
Z......Page 309
Bibliography......Page 310
C......Page 311
N......Page 312
W – X – Y – Z......Page 313
The Author......Page 314