Rapid Prototyping of Digital Systems: SOPC Edition

✍ Scribed by James O. Hamblen, Tyson S. Hall, Michael D. Furman

• Publisher: Springer
• Year: 2007
• Tongue: English
• Leaves: 417
• Edition: 1
• Category: Library

✦ Synopsis

Here is a laboratory workbook filled with interesting and challenging projects for digital logic design and embedded systems classes. The workbook introduces you to fully integrated modern CAD tools, logic simulation, logic synthesis using hardware description languages, design hierarchy, current generation field programmable gate array technology, and SoPC design. Projects cover such areas as serial communications, state machines with video output, video games and graphics, robotics, pipelined RISC processor cores, and designing computer systems using a commercial processor core.

✦ Table of Contents

Front-cover......Page 1
Front-matter......Page 2
Table of Contents......Page 5
PREFACE......Page 13
CHAPTER 1 Tutorial I:The 15-Minute Design......Page 18
CHAPTER 2 FPGA Development Board Hardware and I/O Features......Page 62
CHAPTER 3 Programmable Logic Technology......Page 71
CHAPTER 4 Tutorial II: Sequential Design and Hierarchy......Page 88
CHAPTER 5 FPGAcore Library Functions......Page 101
CHAPTER 6 Using VHDL for Synthesis of Digital Hardware......Page 118
CHAPTER 7 Using Verilog for Synthesis of Digital Hardware......Page 141
CHAPTER 8 State Machine Design: The Electric Train Controller......Page 159
CHAPTER 9 A Simple Computer Design: The μP 3......Page 180
CHAPTER 10 VGA Video Display Generation using FPGAs......Page 202
CHAPTER 11 Interfacing to the PS/2 Keyboard and Mouse......Page 223
CHAPTER 12 Legacy Digital I/O Interfacing Standards......Page 240
CHAPTER 13 FPGA Robotics Projects......Page 250
CHAPTER 14 A RISC Design: Synthesis of the MIPS Processor Core......Page 291
CHAPTER 15 Introducing System-on-a-Programmable-Chip......Page 317
CHAPTER 16 Tutorial III: Nios II Processor Software Development......Page 328
CHAPTER 17 Tutorial IV: Nios II Processor Hardware Design......Page 357
CHAPTER 18 Operating System Support for SOPC Design......Page 379
Appendix A: Generation of Pseudo Random Binary Sequences......Page 397
Appendix B: Quartus II Design and Data File Extensions......Page 399
Appendix C: Common FPGA Pin Assignments......Page 400
Appendix D: ASCII Character Code......Page 402
Glossary......Page 405
Index......Page 413
About the Accompanying DVD......Page 417