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Race-free clocking of CMOS pipelines using a single global clock

โœ Scribed by Renshaw, D.; Lau, C.H.


Book ID
119773445
Publisher
IEEE
Year
1990
Tongue
English
Weight
380 KB
Volume
25
Category
Article
ISSN
0018-9200

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This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V~d, decreasing the supply