✦ LIBER ✦

Quietest: A methodology for selectingIDDQtest vectors

✍ Scribed by Weiwei Mao; Ravi K. Gulati

Book ID: 104635844
Publisher: Springer US
Year: 1992
Tongue: English
Weight: 727 KB
Volume: 3
Category: Article
ISSN: 0923-8174
DOI: 10.1007/bf00135338

No coin nor oath required. For personal study only.

✦ Synopsis

Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (IDDQ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each IDD Q measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for IDD a measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by IDD a measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.

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