Predicting gate oxide reliability from statistical process control nodes in integrated circuit manufacturing — a case study
✍ Scribed by James G. Prendergast; Eamonn Murphy; Malcom Stephenson
- Publisher
- John Wiley and Sons
- Year
- 1997
- Tongue
- English
- Weight
- 118 KB
- Volume
- 13
- Category
- Article
- ISSN
- 0748-8017
No coin nor oath required. For personal study only.
✦ Synopsis
This paper investigates the possibility of transferring the concepts developed for SPC into reliability control of integrated circuits. It employs Taguchi methods and response surface methodology to predict the reliability of a 20 nm gate oxide process using selected critical in line parameters. A Taguchi L 12 design was used as a screening experiment to determine the most critical factors which effect the reliability of the gate oxide dielectric. From this three parameters were selected for use in a central composite face centred array to model their effect on the oxide dielectric reliability using response surface methodology. The reliability of the oxide dielectric was measured using time-dependent dielectric breakdown testing, and the calculations were based on the time to 0•1 per cent cumulative failure, as this is the time on which industry standard reliability predictions are based. The results show that using a test chip the intrinsic reliability of the oxide can be modelled using the values obtained from critical nodes within a wafer fabrication facility and that this is a viable approach to predict oxide reliability.