Planar Double-Gate Transistor: From technology to circuit

✍ Scribed by Amara Amara, Amara Amara, Olivier Rozeau

• Publisher: Springer
• Year: 2009
• Tongue: English
• Leaves: 215
• Edition: 1
• Category: Library

✦ Synopsis

This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring.

Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap.

✦ Table of Contents

Planar Double-Gate Transis......Page 3
Contents......Page 5
Introduction......Page 9
1.1 Introduction......Page 11
1.2 Advantages of Multiple Gate Technologies......Page 12
1.3 Planar Double Gate Technologies......Page 20
1.4 Non Planar Multiple Gate Technologies......Page 24
References......Page 28
2.1 Introduction......Page 34
2.2 Drift-Diffusion Drain Current Modeling......Page 37
2.3 Ballistic Current in the Subthreshold Regime......Page 49
2.4 Conclusion......Page 57
References......Page 58
3.1 Introduction......Page 62
3.2 Modeling of Double Gate MOSFET with Independent Driven Gates......Page 63
3.3 Long Channel IDG Mosfet Threshold Voltage Based Model......Page 67
3.4 Short Channel Effects......Page 84
3.5 Conclusion......Page 90
References......Page 91
4.1 Introduction......Page 96
4.2 Low Frequency Noise Analysis......Page 97
4.3 Results and Discussions......Page 100
References......Page 110
5.1 Double Gate MOSFET in Analog Design......Page 112
5.2 Current Mirrors......Page 116
5.3 Differential Pairs......Page 120
5.4 Low Voltage OTAS......Page 126
5.5 High Speed Comparators......Page 140
References......Page 142
6.1 DGMOS Characteristics and Impact on Digital Design......Page 144
6.2 Standard Cells Using DGMOS......Page 146
6.3 Ultra Low Power Full-Adder using Double Gate SOI Devices......Page 152
6.4 DGMOS DEVICE Based Reconfigurabl Cells......Page 158
References......Page 171
7.1 Introduction......Page 173
7.2 SRAM Memories......Page 175
7.3 Double Gate 6T SRAM Memories......Page 185
7.4 Double Gate 4T & 5T SRAM Memories......Page 201
References......Page 208
Conclusion......Page 210
Abbreviations......Page 212
Index......Page 215