Physical limitations and design for sub-0.1-μm MOS devices: Carrier velocity overshoot and performance fluctuation
✍ Scribed by Tomohisa Mizuno; Ryuji Ohba
- Publisher
- John Wiley and Sons
- Year
- 1998
- Tongue
- English
- Weight
- 153 KB
- Volume
- 81
- Category
- Article
- ISSN
- 8756-663X
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✦ Synopsis
We study the physical limitations of MOSFETs around 0.1 mm and introduce a new scaling scenario for sub-0.1-mm MOS devices. At low transverse electric fields, that is, for low carrier densities in SOI devices under low gate drive conditions, it is possible to achieve electron velocity overshoot due to nonstationary transport in the sub-0.1-mm region. However, it is very difficult in MOS structures to improve electron velocity at high surface electron densities because of the reduced electron mobility in high transverse fields. Moreover, the surface electron density in a MOS structure is reduced when a low channel impurity concentration is chosen to improve low field mobility. These results indicate the physical limitations of scaled MOS structures as regards the realization of higher current capabilities. On the other hand, we show that there is a most suitable channel dopant density for reducing statistical fluctuations in the threshold voltage. We present a new scaling design for sub-0.1-mm MOS devices that achieves both high current drivability and suppressed performance fluctuations.