Cover
Title Page
Copyright
Contents
Preface
About Authors
Chapter 1 Introduction
1.1 Phase‐Lock Technique
1.2 Key Properties and Applications
1.2.1 Frequency Synthesis
1.2.2 Clock‐and‐Data Recovery
1.2.3 Synchronization
1.2.4 Modulation and Demodulation
1.2.5 Carrier Recovery
1.2.6 Frequency Translation
1.3 Organization and Scope of the Book
Bibliography
Part I Phase‐Lock Basics
Chapter 2 Linear Model and Loop Dynamics
2.1 Linear Model of the PLL
2.2 Feedback System
2.2.1 Basics of Feedback Loop
2.2.2 Stability
2.3 Loop Dynamics of the PLL
2.3.1 First‐Order Type 1 PLL
2.3.2 Second‐Order Type 1 PLL
2.3.3 Second‐Order Type 2 PLL
2.3.4 Natural Frequency and Damping Ratio
2.3.5 High‐Order PLLs
2.3.6 Bandwidth of PLL
2.3.7 Loop Gain and Natural Frequency
2.3.8 3‐dB Bandwidth
2.3.9 Noise Bandwidth
2.4 Noise Transfer Function
2.5 Charge‐Pump PLL
2.5.1 High‐Order CP‐PLL
2.5.2 Control of Loop Parameters
2.5.3 Another Role of Shunt Capacitor
2.6 Other Design Considerations
2.6.1 Time‐Continuous Approximation
2.6.2 Practical Design Aspects
References
Chapter 3 Transient Response
3.1 Linear Transient Performance
3.1.1 Steady‐State Phase Response
3.1.2 Transient Phase Response
3.1.3 Settling Time
3.2 Nonlinear Transient Performance
3.2.1 Hold‐In Range
3.2.2 Pull‐In Range
3.2.3 Lock‐In Range
3.2.4 Nonlinear Phase Acquisition
3.3 Practical Design Aspects
3.3.1 Type 1 and Type 2 PLLs with Frequency‐Step Input
3.3.2 State‐Variable Model
3.3.3 Two‐Path Control in the CP‐PLL
3.3.4 Two‐Path Control in DPLL
3.3.5 Slew Rate of CP‐PLL
3.3.6 Effect of the PFD Turn‐On Time
References
Part II System Perspectives
Chapter 4 Frequency and Spectral Purity
4.1 Spur Generation and Modulation
4.1.1 Spurious Signal (Spur)
4.1.1.1 Narrowband FM
4.1.1.2 Generation of a Single Sideband
4.1.1.3 Estimation of Spur Level
4.1.1.4 Deterministic Jitter by Periodic Modulation
4.1.1.5 Effect of Frequency Division and Multiplication
4.1.2 Reference Spur
4.1.2.1 Leakage Current
4.1.2.2 Charge Pump Mismatch
4.1.2.3 PFD Mismatch
4.2 Phase Noise and Random Jitter
4.2.1 Phase Noise Generation and Measurement
4.2.1.1 Spectral Analysis of Real Signal
4.2.1.2 Phase Noise Analysis
4.2.1.3 Spectrum Analyzer
4.2.1.4 Effect of Frequency Division and Multiplication
4.2.2 Integrated Phase Noise
4.2.3 Optimum Loop Bandwidth for Phase Noise
References
Chapter 5 Application Aspects
5.1 Frequency Synthesis
5.1.1 Direct Frequency Synthesis
5.1.2 Indirect Frequency Synthesis by Phase Lock
5.1.3 Frequency Synthesizer Architectures for Fine Resolution
5.1.4 System Design Aspects for Frequency Synthesis
5.2 Clock‐and‐Data Recovery
5.2.1 Wireline Transceiver with Serial Link
5.2.2 Clock Recovery and Data Retiming by PLL
5.2.2.1 Jitter Generation
5.2.2.2 Jitter Transfer
5.2.2.3 Jitter Tolerance
5.2.2.4 Role of Bandwidth and Comparison
5.3 Clock Generation
5.3.1 System Design Aspects
5.3.2 Clock Jitter for Wireline Systems
5.3.2.1 RJ and BER
5.3.2.2 Total Jitter
5.4 Synchronization
5.4.1 PLL for Clock De‐skewing
5.4.2 Delay‐Locked Loop
References
Part III Building Circuits
Chapter 6 Phase Detector
6.1 Non‐Memory Phase Detectors
6.1.1 Multiplier PD
6.1.2 Exclusive‐OR PD
6.1.3 Flip‐Flop PD
6.1.4 Sample‐and‐Hold PD
6.1.5 Sub‐Sampling PD
6.2 Phase‐Frequency Detector
6.2.1 Operation Principle
6.2.2 Dead‐Zone Problem
6.2.3 Effect of the PFD Turn‐On Time on PLL Settling
6.2.4 Noise Performance of PFD
6.3 Charge Pump
6.3.1 Circuit Design Considerations
6.3.1.1 Current Matching, Leakage Current, and Linearity
6.3.1.2 Phase Noise Contribution
6.3.1.3 Design Flow
6.3.2 Single‐Ended Charge Pump Circuits
6.3.3 Semi‐ and Fully Differential Charge Pump Circuits
6.3.4 Design of Differential Loop Filter
References
Chapter 7 Voltage‐Controlled Oscillator
7.1 Oscillator Basics
7.1.1 Oscillation Condition
7.1.2 Quality Factor
7.1.3 Frequency Stability
7.1.4 Effect of Circuit Noise
7.1.5 Leeson's Model and Figure‐of‐Merit
7.1.6 Effect of Noise Coupling
7.2 LC VCO
7.2.1 Design Considerations
7.2.1.1 Oscillation Startup
7.2.1.2 Tuning Range
7.2.1.3 Phase Noise
7.2.2 LC VCO Circuit Topologies
7.2.2.1 Conventional VCO with Cross‐Coupled Pair and Complementary Pair
7.2.2.2 Class‐C VCO
7.2.2.3 Tail Noise Reduction with Common‐Mode Noise Filtering
7.2.2.4 Wide Tuning with Discrete Capacitor Array
7.2.2.5 Seamless Wide Tuning with Single‐Input Dual‐Path Control
7.3 RING VCO
7.3.1 Design Aspects
7.3.2 Phase Noise
7.3.2.1 Single‐Ended Ring Oscillator
7.3.2.2 Differential Ring Oscillator
7.3.3 Circuit Implementation
7.3.3.1 Single‐Ended VCDL
7.3.3.2 Fully Differential VCDL
7.3.3.3 Pseudo‐Differential VCDL
7.4 Relaxation VCO
7.4.1 Relaxation Oscillator with Ground Capacitor
7.4.2 Relaxation Oscillator with Floating Capacitor
References
Chapter 8 Frequency Divider
8.1 Basic Operation
8.1.1 Frequency Division with Prescaler
8.1.2 Standard Configuration of Prescaler‐based Frequency Divider
8.1.3 Operation Principle of Dual‐Modulus Divider
8.2 Circuit Design Considerations
8.2.1 Frequency Divider with Standard Logic Circuits
8.2.2 Frequency Divider with Current‐Mode Logic Circuits
8.2.3 Critical Path of Modulus Control
8.3 Other Topologies
8.3.1 Phase‐Selection Divider
8.3.2 Phase‐Interpolated Fractional‐N Divider
8.3.3 (2k + M) Multi‐Modulus Divider
8.3.4 Regenerative Divider
8.3.4.1 Miller Divider
8.3.4.2 Injection‐Locked Divider
References
Part IV PLL Architectures
Chapter 9 Fractional‐N PLL
9.1 Fractional‐N Frequency Synthesis
9.1.1 Basic Operation
9.1.2 Spur Reduction Methods
9.1.2.1 Phase Compensation by a DAC
9.1.2.2 Phase Compensation by a DTC
9.1.2.3 Multi‐Phase Fractional‐N Division
9.1.2.4 Pseudo‐Random Modulation Method
9.1.2.5 Delta‐Sigma Modulation Method
9.1.3 Multi‐Loop Hybrid Frequency Synthesis
9.2 Frequency Synthesis with Delta‐Sigma Modulation
9.2.1 ΔΣ Modulation
9.2.1.1 ΔΣ ADC and Quantization Noise
9.2.1.2 High‐Order Modulator
9.2.1.3 Cascaded Modulator
9.2.2 All‐Digital ΔΣ Modulators for Fractional‐N Frequency Synthesis
9.2.2.1 MASH Modulator
9.2.2.2 SLDSM with 1‐Bit Quantizer
9.2.2.3 SLDSM with Multi‐Level Quantizer
9.2.3 Phase Noise by Quantization Error
9.2.4 Dynamic Range and Bandwidth
9.2.5 Nonideal Effects
9.2.5.1 Nonlinearity
9.2.5.2 Integer‐Boundary Spur
9.2.6 Practical Design Aspects for the ΔΣ Fractional‐N PLL
9.3 Quantization Noise Reduction Methods
9.3.1 Phase Compensation
9.3.2 Noise Filtering
9.4 Frequency Modulation by Fractional‐N PLL
9.4.1 One‐Point Modulation
9.4.2 Two‐Point Modulation
References
Chapter 10 Digital‐Intensive PLL
10.1 DPLL with Linear TDC
10.1.1 Loop Dynamics
10.1.1.1 Time‐Continuous Approximation
10.1.1.2 CP‐PLL Analogy
10.1.2 TDC
10.1.2.1 Time Resolution and Phase Noise
10.1.2.2 Enhanced Architectures and Variations
10.1.3 DCO
10.1.3.1 Basic Architectures
10.1.3.2 Phase Noise Due to Quantization
10.2 DPLL with 1‐Bit TDC
10.2.1 Loop Behavior of BB‐DPLL
10.2.1.1 Limit‐Cycle Regime
10.2.1.2 Random‐Noise Regime
10.2.2 Fractional‐N BB‐DPLL
10.2.3 Different Design Aspects of BB‐DPLL
10.2.3.1 SLDSM versus MASH Modulation
10.2.3.2 Two‐Stage versus Single‐Stage Topology
10.2.3.3 Effect of Phase‐Domain Low‐Pass Filter
10.2.3.4 Two‐Point versus One‐Point Modulation
10.3 Hybrid PLL
10.3.1 Hybrid Loop Control
10.3.2 Design Aspects of the HPLL
References
Chapter 11 Clock‐and‐Data Recovery PLL
11.1 Loop Dynamics Considerations for CDR
11.1.1 JGEN and Noise Sources
11.1.2 JTRAN and Jitter Peaking
11.1.3 JTOR and Jitter Tracking
11.2 CDR PLL Architectures Based on Phase Detection
11.2.1 CDR with Linear Phase Detection
11.2.1.1 Phase Detection with NRZ Data
11.2.1.2 Hogge PD
11.2.2 CDR with Binary Phase Detection
11.2.2.1 Binary Phase Detection Using a DFF
11.2.2.2 Alexander PD
11.2.2.3 Half‐Rate Alexander PD
11.2.3 CDR with Baud‐Rate Phase Detection
11.3 Frequency Acquisition
11.3.1 Frequency Detector
11.3.2 CDR PLL with Frequency Acquisition Aid Circuits
11.4 DLL‐assisted CDR Architectures
11.4.1 Delay‐ and Phase‐Locked Loop (D/PLL)
11.4.2 Phase‐ and Delay‐Locked Loop (P/DLL)
11.4.3 Digital DLL with Phase Rotation
11.5 Open‐Loop CDR Architectures
11.5.1 Blind Oversampling CDR
11.5.2 Burst‐Mode CDR
References
Index
EULA