Peripheral loss reduction of high efficiency silicon solar cells by MOS gate passivation, by poly-Si filled grooves and by cell pattern design
✍ Scribed by Jianhua Zhao; Aihua Wang; Pietro P. Altermatt; Guangchun Zhang
- Publisher
- John Wiley and Sons
- Year
- 2000
- Tongue
- English
- Weight
- 203 KB
- Volume
- 8
- Category
- Article
- ISSN
- 1062-7995
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✦ Synopsis
This paper reports a variety of methods to reduce the peripheral or edge losses in high eciency silicon PERL (Passivated Emitter, Rear Locally-diused) cells. A MOS (Metal Oxide Semiconductor) structure was investigated as a way to passivate the peripheral region of high eciency PERL silicon solar cells, when this region is shaded during cell measurement. A marginal gain in the cell short-circuit current has been observed when a positive voltage is applied to the MOS gate at the cell peripheral region. When a negative bias is applied to the gate, a current loss, a signi®cant gain in the cell ®ll factors and a marginal gain in cell eciency have been observed. Two-dimensional numerical modelling has been used to analyse this performance. Although the model has predicted a similar trend, it can not fully ®t to the experimental data. A weakly inverted surface channel may have resulted in the ®ll factor change. A higher eciency gain is predicted if the surface channel can be eliminated.
Other experimental methods to passivate scribed PERL cells are also discussed in this paper. Laser-cut grooves ®lled with poly-silicon at the cell edges have resulted in an improved cell performance after cell peripheral regions have been scribed o. Special design of the cells for a shingled array application has also signi®cantly improved the cell performance, and made it possible to demonstrate 23 . 7% eciency on a 21 . 6 cm 2 large area, scribed silicon cell.