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Performance evaluation of a bus-based multistage multiprocessor architecture

✍ Scribed by A. Veglis; A. Pombortsis; E. Papaefstathiou


Publisher
Elsevier Science
Year
2000
Tongue
English
Weight
370 KB
Volume
46
Category
Article
ISSN
1383-7621

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As microprocessors become faster and demand more bandwidth, the already limited scalability of a shared bus decreases even further. DICE, a shared-bus multiprocessor, utilizes cache only memory architecture (COMA) to effectively decrease the speed gap between modern high-performance microprocessors